Sysctl.txt

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Sysctl.txt[edit]

Inside CoreOS in old versions. Moved inside lv1.self since 090.002 - DECR. See also: Repository Nodes, HV Syscall Reference

Samples[edit]

r9460 083.006.r010 2_E 060.013.r010 / 2_I 050.003
sys.lv1.iosys.storage = 1
sys.lv1_systemspu.mode = 0
sys.lv1.iosys.errorhandler = 0
lv1.heap.afill = 0
lv1.heap.rfill = 0
sys.lv1console.mode = 0
sys.lv1.emuioif0irq = 0
sys.lv1.rsxenable = 2
sys.lv1.rsxdebug = 1
sys.lv1.be_ras = 0
sys.lv1.iofaultmsg = 0
sys.mmio.map_allow = 2
sys.pci.share = 0
be.0.fir.ras_ee = 0xffffffff
be.0.fir.l2_em = 0x0
be.0.fir.l2_ee = 0xeff81
be.0.fir.biu_em = 0x0
be.0.fir.biu_ee = 0xff
be.0.fir.ciu_em = 0x0
be.0.fir.ciu_ee = 0x3fe0000000000000
be.0.fir.mic_f0 = 0x0000fd7e00000000
be.0.fir.mic_f1 = 0x0000028000000000
be.0.fir.ioc_em = 0x0
be.0.fir.ioc_ee = 0x70fb0fb03f03f0f
be.0.fir.spu0_em = 0x1bf7ff
be.0.fir.spu0_ee = 0x0
be.0.fir.spu1_em = 0x1bf7ff
be.0.fir.spu1_ee = 0x0
be.0.fir.spu2_em = 0x1bf7ff
be.0.fir.spu2_ee = 0x0
be.0.fir.spu3_em = 0x1bf7ff
be.0.fir.spu3_ee = 0x0
be.0.fir.spu4_em = 0x1bf7ff
be.0.fir.spu4_ee = 0x0
be.0.fir.spu5_em = 0x1bf7ff
be.0.fir.spu5_ee = 0x0
be.0.fir.spu6_em = 0x1bf7ff
be.0.fir.spu6_ee = 0x0
be.0.fir.spu7_em = 0x1bf7ff
be.0.fir.spu7_ee = 0x0
be.0.lpm.lpar = 2
be.0.lpm.priv = 0x600301
lv1.ram.enable = 1
lv1.ram.spe_ragid = 2
lv1.ram.tkm_cr = 0x000f73e0
lv1.ram.tkm_mbar = 0x057d150e
lv1.ram.tkm_ioif0_ar = 0x00fc79cb
lv1.ram.tkm_ioif1_ar = 0
lv1.ram.tkm_pr = 0x3ffffffff
lv1.ram.mic_tm_threshold_0 = 0x86390c7000000000
lv1.ram.mic_tm_threshold_1 = 0x86390c7000000000
lv1.ram.ioc_ioif0_quethshld = 0x676700
lv1.ram.ioc_ioif1_quethshld = 0
lv1.ram.biu_modesetup1 = 0xf003c00000000000
lv1.ram.biu_modesetup2 = 0x000003c020000500
sys.lv1.iosys.storage = 1
sys.lv1_systemspu.mode = 0
sys.lv1.iosys.errorhandler = 0
lv1.heap.afill = 0
lv1.heap.rfill = 0
sys.lv1console.mode = 0
sys.lv1.emuioif0irq = 0
sys.lv1.rsxenable = 2
sys.lv1.rsxdebug = 0
sys.lv1.be_ras = 0
sys.lv1.iofaultmsg = 0
sys.mmio.map_allow = 2
sys.pci.share = 0
be.0.fir.ras_ee = 0xffffffff
be.0.fir.l2_em = 0x0
be.0.fir.l2_ee = 0xeff81
be.0.fir.biu_em = 0x0
be.0.fir.biu_ee = 0xff
be.0.fir.ciu_em = 0x0
be.0.fir.ciu_ee = 0x3fe0000000000000
be.0.fir.mic_f0 = 0x0000fd7e00000000
be.0.fir.mic_f1 = 0x0000028000000000
be.0.fir.ioc_em = 0x0
be.0.fir.ioc_ee = 0x70fb0fb03f03f0f
be.0.fir.spu0_em = 0x1bf7ff
be.0.fir.spu0_ee = 0x0
be.0.fir.spu1_em = 0x1bf7ff
be.0.fir.spu1_ee = 0x0
be.0.fir.spu2_em = 0x1bf7ff
be.0.fir.spu2_ee = 0x0
be.0.fir.spu3_em = 0x1bf7ff
be.0.fir.spu3_ee = 0x0
be.0.fir.spu4_em = 0x1bf7ff
be.0.fir.spu4_ee = 0x0
be.0.fir.spu5_em = 0x1bf7ff
be.0.fir.spu5_ee = 0x0
be.0.fir.spu6_em = 0x1bf7ff
be.0.fir.spu6_ee = 0x0
be.0.fir.spu7_em = 0x1bf7ff
be.0.fir.spu7_ee = 0x0
be.0.lpm.lpar = 2
be.0.lpm.priv = 0x600301
lv1.ram.enable = 1
lv1.ram.spe_ragid = 2
lv1.ram.tkm_cr = 0x000f73e0
lv1.ram.tkm_mbar = 0x057d150e
lv1.ram.tkm_ioif0_ar = 0x00fc79cb
lv1.ram.tkm_ioif1_ar = 0
lv1.ram.tkm_pr = 0x3ffffffff
lv1.ram.mic_tm_threshold_0 = 0x86390c7000000000
lv1.ram.mic_tm_threshold_1 = 0x86390c7000000000
lv1.ram.ioc_ioif0_quethshld = 0x676700
lv1.ram.ioc_ioif1_quethshld = 0
lv1.ram.biu_modesetup1 = 0xf003c00000000000
lv1.ram.biu_modesetup2 = 0x000003c020000500
lv1.heap.afill = 0
lv1.heap.rfill = 0
sys.lv1console.mode = 0
sys.lv1.emuioif0irq = 0
sys.lv1.rsxenable = 2
sys.lv1.rsxdebug = 0
sys.mmio.map_allow = 0
sys.pci.share = 0
be.0.fir.ras_ee = 0xffffffff
be.0.fir.l2_em = 0x0
be.0.fir.l2_ee = 0xeff81
be.0.fir.biu_em = 0x0
be.0.fir.biu_ee = 0xff
be.0.fir.ciu_em = 0x0
be.0.fir.ciu_ee = 0x3fe0000000000000
be.0.fir.mic_f0 = 0xffe0000
be.0.fir.mic_f1 = 0x280000000000000
be.0.fir.ioc_em = 0x0
be.0.fir.ioc_ee = 0x70fb0fb03f03f0f
be.0.fir.spu0_em = 0x1bf7ff
be.0.fir.spu0_ee = 0x0
be.0.fir.spu1_em = 0x1bf7ff
be.0.fir.spu1_ee = 0x0
be.0.fir.spu2_em = 0x1bf7ff
be.0.fir.spu2_ee = 0x0
be.0.fir.spu3_em = 0x1bf7ff
be.0.fir.spu3_ee = 0x0
be.0.fir.spu4_em = 0x1bf7ff
be.0.fir.spu4_ee = 0x0
be.0.fir.spu5_em = 0x1bf7ff
be.0.fir.spu5_ee = 0x0
be.0.fir.spu6_em = 0x1bf7ff
be.0.fir.spu6_ee = 0x0
be.0.fir.spu7_em = 0x1bf7ff
be.0.fir.spu7_ee = 0x0
be.0.lpm.lpar = 0x3
be.0.lpm.priv = 0x600301
lv1.ram.enable = 0
lv1.ram.ppe_ragid = 0
lv1.ram.spe_ragid = 0
lv1.ram.tkm_cr = 0x000fb61f
lv1.ram.tkm_mbar = 0x07ffffff
lv1.ram.tkm_ioif0_ar = 0x3fffffff3fffffff
lv1.ram.tkm_ioif1_ar = 0x11ffffff12ffffff
lv1.ram.tkm_pr = 0x3ffffffff
lv1.ram.mic_tm_threshold_0 = 0x3bf077e000000000
lv1.ram.mic_tm_threshold_1 = 0x3bf077e000000000
lv1.ram.ioc_ioif0_quethshld = 0
lv1.ram.ioc_ioif1_quethshld = 0
#pme.console.split = 1
lv1.heap.afill = 0
lv1.heap.rfill = 0
sys.lv1console.mode = 0
sys.lv1.emuioif0irq = 0
sys.lv1.rsxenable = 1
sys.lv1.rsxdebug = 0
sys.mmio.map_allow = 0
sys.pci.share = 0
be.0.fir.ras_ee = 0xffffffff
be.0.fir.l2_em = 0x0
be.0.fir.l2_ee = 0xeff81
be.0.fir.biu_em = 0x0
be.0.fir.biu_ee = 0xff
be.0.fir.ciu_em = 0x0
be.0.fir.ciu_ee = 0x3fe0000000000000
be.0.fir.mic_f0 = 0xffe0000
be.0.fir.mic_f1 = 0x280000000000000
be.0.fir.ioc_em = 0x0
be.0.fir.ioc_ee = 0x70fb0fb03f03f0f
be.0.fir.spu0_em = 0x1bf7ff
be.0.fir.spu0_ee = 0x0
be.0.fir.spu1_em = 0x1bf7ff
be.0.fir.spu1_ee = 0x0
be.0.fir.spu2_em = 0x1bf7ff
be.0.fir.spu2_ee = 0x0
be.0.fir.spu3_em = 0x1bf7ff
be.0.fir.spu3_ee = 0x0
be.0.fir.spu4_em = 0x1bf7ff
be.0.fir.spu4_ee = 0x0
be.0.fir.spu5_em = 0x1bf7ff
be.0.fir.spu5_ee = 0x0
be.0.fir.spu6_em = 0x1bf7ff
be.0.fir.spu6_ee = 0x0
be.0.fir.spu7_em = 0x1bf7ff
be.0.fir.spu7_ee = 0x0
be.0.lpm.lpar = 0x3
be.0.lpm.priv = 0x600301
lv1.ram.enable = 0
lv1.ram.ppe_ragid = 0
lv1.ram.spe_ragid = 0
lv1.ram.tkm_cr = 0x000fb61f
lv1.ram.tkm_mbar = 0x07ffffff
lv1.ram.tkm_ioif0_ar = 0x3fffffff3fffffff
lv1.ram.tkm_ioif1_ar = 0x11ffffff12ffffff
lv1.ram.tkm_pr = 0x3ffffffff
lv1.ram.mic_tm_threshold_0 = 0x3bf077e000000000
lv1.ram.mic_tm_threshold_1 = 0x3bf077e000000000
lv1.ram.ioc_ioif0_quethshld = 0
lv1.ram.ioc_ioif1_quethshld = 0
lv1.heap.afill = 0
lv1.heap.rfill = 0
sys.lv1console.mode = 0
sys.mmio.map_allow = 0
sys.pci.share = 0
be.0.fir.ras_ee = 0xffffffff
be.0.fir.l2_em = 0x0
be.0.fir.l2_ee = 0xeff81
be.0.fir.biu_em = 0x0
be.0.fir.biu_ee = 0xff
be.0.fir.ciu_em = 0x0
be.0.fir.ciu_ee = 0x3fe0000000000000
be.0.fir.mic_f0 = 0xffe0000
be.0.fir.mic_f1 = 0x280000000000000
be.0.fir.ioc_em = 0x0
be.0.fir.ioc_ee = 0x70fb0fb03f03f0f
be.0.fir.spu0_em = 0x1bf7ff
be.0.fir.spu0_ee = 0x0
be.0.fir.spu1_em = 0x1bf7ff
be.0.fir.spu1_ee = 0x0
be.0.fir.spu2_em = 0x1bf7ff
be.0.fir.spu2_ee = 0x0
be.0.fir.spu3_em = 0x1bf7ff
be.0.fir.spu3_ee = 0x0
be.0.fir.spu4_em = 0x1bf7ff
be.0.fir.spu4_ee = 0x0
be.0.fir.spu5_em = 0x1bf7ff
be.0.fir.spu5_ee = 0x0
be.0.fir.spu6_em = 0x1bf7ff
be.0.fir.spu6_ee = 0x0
be.0.fir.spu7_em = 0x1bf7ff
be.0.fir.spu7_ee = 0x0
be.0.lpm.lpar = 0x3
be.0.lpm.priv = 0x600301