Editing Documented SPU Channels

== List of channels ==
{| class="wikitable"
|-
!Channel Name
!Number (hex)
!Notes
|-
|SPU Write Outbound Interrupt Mailbox
|0x1E
|
|-
|SPU Read Inbound Mailbox
|0x1D
|
|-
|SPU Write Outbound Mailbox
|0x1C
|
|-
|MFC Read Atomic Command Status
|0x1B
|
|-
|MFC Write List Stall-and-Notify Tag Acknowledgment
|0x1A
|
|-
|MFC Read List Stall-and-Notify Tag Status
|0x19
|
|-
|MFC Read Tag Group Status
|0x18 
|
|-
|MFC Write Tag Status Update Request
|0x17 
|
|-
|MFC Write Tag Group Query Mask
|0x16 
|
|-
|MFC Command Opcode
|0x15 
|lower 16 bits
|-
|MFC Class ID
|0x15 
|upper 16 bits
|-
|MFC Tag ID
|0x14 
|
|-
|MFC Transfer Size or List Size
|0x13 
|
|-
|MFC Effective Address Low or List Address
|0x12 
|
|-
|MFC Effective Address High
|0x11 
|
|-
|MFC LS Address
|0x10 
|
|-
|SPU Read State Save-and-Restore
|0xF 
|
|-
|SPU Write State Save-and-Restore
|0xE 
|
|-
|SPU Read Machine Status
|0xD 
|
|-
|MFC Read Tag Group Query Mask Channel
|0xC 
|
|-
|SPU Read Event Mask
|0xB 
|
|-
|MFC Write Multisource Synchronization Request
|0x9 
|
|-
|SPU Read Decrementer
|0x8 
|
|-
|SPU Write Decrementer
|0x7 
|
|-
|SPU Signal Notification 2
|0x4 
|
|-
|SPU Signal Notification 1
|0x3 
|
|-
|SPU Write Event Acknowledgment
|0x2 
|
|-
|SPU Write Event Mask
|0x1 
|
|-
|SPU Read Event Status
|0x0 
|
|-
|}

* The rest of the 64 channels are reserved.
* There is a total of 128 channels (some of them are [[Documented SPU Channels]] and some others are [[Undocumented SPU Channels]])

=== Resources ===
* http://www.ibm.com/developerworks/library/pa-celldmas/
: ''The MFC is discussed in Section 6 of [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/1AEEE1270EA2776387257060006E61BA/$file/CBEA_v1.02_11Oct2007_pub.pdf Cell Broadband Engine Architecture V1.0], while the first 27 DMA channels are listed in the [http://www.diku.dk/~rehr/cell/docs/SPU_language_extensions_2.1.pdf SPU C/C++ Language Extensions V2.0]''

{{Development}}<noinclude>[[Category:Main]]</noinclude>