Template:Metbootldr: Difference between revisions

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(Fixed the template and the lowest DECR-1000 version.)
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{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
{| border="1" cellspacing="0" cellpadding="5" border="#999" class="wikitable" style="border:1px solid #999; border-collapse: collapse;"  
|- bgcolor="#cccccc"
|- bgcolor="#cccccc"
! [[IDPS]]/[[Target_ID]] !! rowspan="2" | [[SKU_Models#Datecode_.2F_Manufacturing_Date|SKU - Datecode / Manufacturing date]] !! colspan="2" | [[Flash:asecure_loader|metldr offset]] !! colspan="3" | [[Flash:bootldr|bootldr]] !! rowspan="2" | Notes !! rowspan="2" | [[Talk:Playstation_Update_Package_%28PUP%29#Using_fake_upgrade_to_get_lowest_firmware_version_info|low<br />ver<br />chk]]
! [[IDPS]]/[[Target_ID]] !! rowspan="2" | [[SKU_Models#Datecode_.2F_Manufacturing_Date|SKU - Datecode / Manufacturing date]] !! colspan="2" | [[Flash:asecure_loader|metldr offset]] !! colspan="3" | [[Flash:bootldr|bootldr]] !! rowspan="2" | Notes !! rowspan="2" | [[Talk:Playstation_Update_Package_%28PUP%29#Using_fake_upgrade_to_get_lowest_firmware_version_info|lowest<br />known<br />firmware]]
|-
|-
! <small>0x2F077&nbsp;(NOR)<br />0x80877&nbsp;(NAND)</small> !! <small>0x81E&nbsp;(NOR)<br />0x4081E&nbsp;(NAND)</small> !! <small>0x842&nbsp;(NOR)<br />0x40842&nbsp;(NAND)</small> !! <small><abbr title="( header * 0x10 ) + 0x40 = size">size</abbr></small> !! <small>0xFC0002&nbsp;(NOR)<br />0x02&nbsp;(NAND)</small> !! <small>0xFC0012&nbsp;(NOR)<br />0x12&nbsp;(NAND)</small>
! <small>0x2F077&nbsp;(NOR)<br />0x80877&nbsp;(NAND)</small> !! <small>0x81E&nbsp;(NOR)<br />0x4081E&nbsp;(NAND)</small> !! <small>0x842&nbsp;(NOR)<br />0x40842&nbsp;(NAND)</small> !! <small><abbr title="( header * 0x10 ) + 0x40 = size">size</abbr></small> !! <small>0xFC0002&nbsp;(NOR)<br />0x02&nbsp;(NAND)</small> !! <small>0xFC0012&nbsp;(NOR)<br />0x12&nbsp;(NAND)</small>
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| style="text-align:center;" | 01 || [[DEH-Z1010]]&nbsp;([[TMU-520#TMU-520|TMU-520]])&nbsp;{{SD}}|| style="text-align:center;" | 14 20 || style="text-align:center;" | 11 3E || style="text-align:center;" | 2D020 || style="text-align:center;" | 2C FE || style="text-align:center;" | 2C FE || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.80.004</span><!--// metldr rev key: EC3997BBEFFCA7497E70526F BL rev key: 805BF2D9ACD20061B699BB96  Mathieulh-2012-12-16 Metldr/bl are 00 Paired  Different keysets are being used on sysdbg firmwares//-->
| style="text-align:center;" | 01 || [[DEH-Z1010]]&nbsp;([[TMU-520#TMU-520|TMU-520]])&nbsp;{{SD}}|| style="text-align:center;" | 14 20 || style="text-align:center;" | 11 3E || style="text-align:center;" | 2D020 || style="text-align:center;" | 2C FE || style="text-align:center;" | 2C FE || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.80.004</span><!--// metldr rev key: EC3997BBEFFCA7497E70526F BL rev key: 805BF2D9ACD20061B699BB96  Mathieulh-2012-12-16 Metldr/bl are 00 Paired  Different keysets are being used on sysdbg firmwares//-->
|-
|-
| style="text-align:center;" | 01 || [[DECR-1000]]&nbsp;([[TMU-520#TMU-520|TMU-520]])&nbsp;{{DECR}} Every DECR manufactured before January 2009 Share the same BL/Metldr revisions || style="text-align:center;" | EC 40 || style="text-align:center;" | 0E C0 || style="text-align:center;" | 2A840 || style="text-align:center;" | 2A 80 || style="text-align:center;" | 2A 80 || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.85.009</span><!--// metldr rev key: 664566FA7788F8432FB7AA62 BL rev key: 444890DD192C912DBB996FC8  Mathieulh-2012-12-16 //-->
| style="text-align:center;" | 01 || [[DECR-1000]]&nbsp;([[TMU-520#TMU-520|TMU-520]])&nbsp;{{DECR}} Every DECR manufactured before January 2009 Share the same BL/Metldr revisions || style="text-align:center;" | EC 40 || style="text-align:center;" | 0E C0 || style="text-align:center;" | 2A840 || style="text-align:center;" | 2A 80 || style="text-align:center;" | 2A 80 || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.85.010</span><!--// metldr rev key: 664566FA7788F8432FB7AA62 BL rev key: 444890DD192C912DBB996FC8  Mathieulh-2012-12-16 //-->
|-
|-
| style="text-align:center;" | 01 || ?DEH-H1001-D?&nbsp;([[COK-00x#COK-001|COOKIE13]])&nbsp;{{CEX}} || style="text-align:center;" | EC 40 || style="text-align:center;" | 0E C0 || style="text-align:center;" | 2A830 || style="text-align:center;" | 2A 7F || style="text-align:center;" | 2A 7F || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.85.009</span><!--// 00 00 00 01 00 83 00 01 10 00 00 5A 17 CD E0 F5  SkyDrive-2012-12-04\COOKIE-13 //-->
| style="text-align:center;" | 01 || ?DEH-H1001-D?&nbsp;([[COK-00x#COK-001|COOKIE13]])&nbsp;{{CEX}} || style="text-align:center;" | EC 40 || style="text-align:center;" | 0E C0 || style="text-align:center;" | 2A830 || style="text-align:center;" | 2A 7F || style="text-align:center;" | 2A 7F || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;=0.85.010</span><!--// 00 00 00 01 00 83 00 01 10 00 00 5A 17 CD E0 F5  SkyDrive-2012-12-04\COOKIE-13 //-->
|-
|-
| style="text-align:center;" | 01 || [[DEH-H1000A-E]]&nbsp;([[COK-00x#COK-001|COK-001]])&nbsp;{{DEX}} || style="text-align:center;" | EC 70 || style="text-align:center;" | 0E C3 || style="text-align:center;" | 2A1E0 || style="text-align:center;" | 2A 1A || style="text-align:center;" | 2A 1A || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;095.001</span><!--// Strike Venom-2012-12-16 //--> <!-- The revision of the met-/bootldr is newer, as these console's were only used by Sony for there Tech-Demos and have been updated (several?) times to match the current state of development. Source: Old SDK info's refer to an system update/upgrade that remove's the ability to downgrade below a specific value. (It refer's to DEH-R... and a factory software upgrade) So there's no way to get the original data :(-->
| style="text-align:center;" | 01 || [[DEH-H1000A-E]]&nbsp;([[COK-00x#COK-001|COK-001]])&nbsp;{{DEX}} || style="text-align:center;" | EC 70 || style="text-align:center;" | 0E C3 || style="text-align:center;" | 2A1E0 || style="text-align:center;" | 2A 1A || style="text-align:center;" | 2A 1A || <span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">&lt;095.001</span><!--// Strike Venom-2012-12-16 //--> <!-- The revision of the met-/bootldr is newer, as these console's were only used by Sony for there Tech-Demos and have been updated (several?) times to match the current state of development. Source: Old SDK info's refer to an system update/upgrade that remove's the ability to downgrade below a specific value. (It refer's to DEH-R... and a factory software upgrade) So there's no way to get the original data :(-->
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| style="text-align:center;" | 03 || [[CECHCxx|CECHCxx]]&nbsp;([[COK-00x#COK-002|COK-002]]) with 1.00&nbsp;from&nbsp;factory || style="text-align:center;" | EB F0 || style="text-align:center;" | 0E BB || style="text-align:center;" | 30480 || style="text-align:center;" | 30 44 || style="text-align:center;" | 30 44 || <!--//euss: CECHC04 NAND FAT//--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">1.00</span><br /><span style="background-color:#30C030; color:white;">1.00</span>
| style="text-align:center;" | 03 || [[CECHCxx|CECHCxx]]&nbsp;([[COK-00x#COK-002|COK-002]]) with 1.00&nbsp;from&nbsp;factory || style="text-align:center;" | EB F0 || style="text-align:center;" | 0E BB || style="text-align:center;" | 30480 || style="text-align:center;" | 30 44 || style="text-align:center;" | 30 44 || <!--//euss: CECHC04 NAND FAT//--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">1.00</span><br /><span style="background-color:#30C030; color:white;">1.00</span>
|-
|-
| style="text-align:center;" | 01<br />03 || [[CECHAxx|CECHAxx]]&nbsp;([[COK-00x#COK-001|COK-001]])<br />[[CECHCxx|CECHCxx]]&nbsp;([[COK-00x#COK-002|COK-002]]) || style="text-align:center;" | ED E0 || style="text-align:center;" | 0E DA || style="text-align:center;" | 2A3B0 || style="text-align:center;" | 2A 37 || style="text-align:center;" | 2A 37 || <!--//meisterma-NAND-370a CECHC04 //--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">1.00</span><br /><span style="background-color:#30C030; color:white;">1.00</span>
| style="text-align:center;" | 01<br />02<br />03 || [[CECHAxx|CECHAxx]]&nbsp;([[COK-00x#COK-001|COK-001]])<br />[[CECHBxx|CECHBxx]]&nbsp;([[COK-00x#COK-001|COK-001]])<br />[[CECHCxx|CECHCxx]]&nbsp;([[COK-00x#COK-002|COK-002]]) || style="text-align:center;" | ED E0 || style="text-align:center;" | 0E DA || style="text-align:center;" | 2A3B0 || style="text-align:center;" | 2A 37 || style="text-align:center;" | 2A 37 || <!--//meisterma-NAND-370a CECHC04 //--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">1.00</span><br /><span style="background-color:#30C030; color:white;">1.00</span><br /><span style="background-color:#30C030; color:white;">1.00</span>
|-
|-
| style="text-align:center;" | 04<br />05 || [[Namco System 357]]&nbsp;([[COK-00x#COK-002|COK-002]])&nbsp;{{ARC}}<br />[[CECHGxx|CECHGxx]]&nbsp;([[SEM-00x|SEM-001]]) || style="text-align:center;" | E7 B0 || style="text-align:center;" | 0E 77 || style="text-align:center;" | 2E900 || style="text-align:center;" | 2E 8C || style="text-align:center;" | 2E 8C || <!--//john__: NAND FAT SEM-001//--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">?1.90?<br />1.90</span>
| style="text-align:center;" | 04<br />05 || [[Namco System 357]]&nbsp;([[COK-00x#COK-002|COK-002]])&nbsp;{{ARC}}<br />[[CECHGxx|CECHGxx]]&nbsp;([[SEM-00x|SEM-001]]) || style="text-align:center;" | E7 B0 || style="text-align:center;" | 0E 77 || style="text-align:center;" | 2E900 || style="text-align:center;" | 2E 8C || style="text-align:center;" | 2E 8C || <!--//john__: NAND FAT SEM-001//--><span style="color:#30C030; background-color:#FFFFFF; ">Patch + FSM = OK</span> || style="background-color:#30C030; color:white;" | <span style="background-color:#30C030; color:white;">?1.90?<br />1.90</span>

Revision as of 18:04, 20 February 2017

You can check metldr and bootldr sizes easily with HxD

  • either after extracting flash with Flowrebuilder and opening seperate files
  • or by looking in the unextracted Flash dump at the correct offset.

This table lists some common known values for your convenience as quick lookup:

IDPS/Target_ID SKU - Datecode / Manufacturing date metldr offset bootldr Notes lowest
known
firmware
0x2F077 (NOR)
0x80877 (NAND)		 0x81E (NOR)
0x4081E (NAND)		 0x842 (NOR)
0x40842 (NAND)		 size 0xFC0002 (NOR)
0x02 (NAND)		 0xFC0012 (NOR)
0x12 (NAND)
n/a CEB-2030 (MPU-501)  PROTO  n/a n/a 28C20 28 BE 28 BE Patch + FSM = OK <=0.50.003
01 DEH-Z1010 (TMU-520)  SD  14 20 11 3E 2D020 2C FE 2C FE Patch + FSM = OK <=0.80.004
01 DECR-1000 (TMU-520)  DECR  Every DECR manufactured before January 2009 Share the same BL/Metldr revisions EC 40 0E C0 2A840 2A 80 2A 80 Patch + FSM = OK <=0.85.010
01 ?DEH-H1001-D? (COOKIE13)  CEX  EC 40 0E C0 2A830 2A 7F 2A 7F Patch + FSM = OK <=0.85.010
01 DEH-H1000A-E (COK-001)  DEX  EC 70 0E C3 2A1E0 2A 1A 2A 1A Patch + FSM = OK <095.001
01
04		 CECHAxx (COK-001)
CECHExx (COK-002)		 EE 10 0E DD 2A430 2A 3F 2A 3F Patch + FSM = OK 1.00
1.00
01
02
03
01		 CECHAxx (COK-001) with 1.00 from factory
CECHBxx (COK-001)
CECHCxx (COK-002)
DECHAxx (COK-001)  DEX 		 ED A0 0E D6 2A2E0 2A 2A 2A 2A Patch + FSM = OK 1.00
1.00
1.00
1.00
03 CECHCxx (COK-002) with 1.00 from factory EB F0 0E BB 30480 30 44 30 44 Patch + FSM = OK 1.00
1.00
01
02
03		 CECHAxx (COK-001)
CECHBxx (COK-001)
CECHCxx (COK-002)		 ED E0 0E DA 2A3B0 2A 37 2A 37 Patch + FSM = OK 1.00
1.00
1.00
04
05		 Namco System 357 (COK-002)  ARC 
CECHGxx (SEM-001)		 E7 B0 0E 77 2E900 2E 8C 2E 8C Patch + FSM = OK ?1.90?
1.90
05
06		 CECHGxx (SEM-001)
CECHHxx (DIA-001)		 E7 B0 0E 77 2F200 2F 1C 2F 1C Patch + FSM = OK 2.30
2.30
05
06		 CECHGxx (SEM-001)
CECHHxx (DIA-001)		 E8 C0 0E 88 2EF80 2E F4 2E F4 Patch + FSM = OK 2.30
2.30
06
07		 CECHHxx (DIA-001)
CECHJxx (DIA-002) with 2.30 from factory - datecode 8B		 E8 E0 0E 8A 2EF80 2E F4 2E F4 Patch + FSM = OK 1.97
2.30
03
06
06		 CECHExx (COK-002)
CECHHxx (DIA-001)
CECHMxx (DIA-001)		 EA 60 0E A2 2EE70 2E E3 2E E3 Patch + FSM = OK
1.97
1.97
07 CECHJxx (DIA-002)
CECHKxx (DIA-002) datecode 8C		 EA 60 0E A2 2EE70 2E E3 2E E3 Patch + FSM = OK
2.30
08
07
08		 Namco System 357 (VER-001)  ARC 
DECHJxx (DIA-002)  DEX 
CECHLxx / CECHPxx (VER-001)		 E8 D0 0E 89 2EAF0 2E AB 2E AB Patch + FSM = OK ?2.45?
2.16
2.45
08 CECHLxx (VER-001) E8 D0 0E 89 2EB70 2E B3 2E B3 Patch + FSM = OK 2.45
08
09		 CECHLxx (VER-001) with 2.30 from factory - datecode unknown
CECH-20xx (DYN-001) with 2.76 from factory, datecode unknown		 E8 90 0E 85 2F170 2F 13 2F 13 Patch + FSM = OK 2.30
2.70
09 DECR-1400 (DEB-001)  DECR  with 2.60 from factory - manufacture date June 09
 E8 90 0E 85 2F170 2F 13 2F 13 Patch + FSM = OK 2.60
09 CECH-20xx (DYN-001) E9 20 0E 8E 2F3F0 2F 3B 2F 3B Patch + FSM = OK 2.70
0A CECH-21xx (SUR-001) E9 20 0E 8E 2F4F0 2F 4B 2F 4B Patch + FSM = OK 3.20
03
0B
0B		 CECHExx (COK-002W) refurbished
CECH-25xx (JTP-001) with 3.40 from factory - datecode 0C
CECH-25xx (JSD-001) with 3.41 from factory - datecode 0C		 E9 20 0E 8E 2F4F0 2F 4B 2F 4B Patch + FSM = OK 3.40
3.40
3.40
0B
0B		 CECH-25xx (JSD-001) with 3.56 from factory - datecode 0D
CECH-25xx (JTP-001) with 3.56 from factory - datecode 1A		 E9 60 0E 92 2F570 2F 53 2F 53 Patch + FSM = OK 3.50
3.50
0B
0B
0B
 CECH-25xx (JTP-001) with 3.56 from factory - datecode 1A (rare)
CECH-25xx (JSD-001) with 3.56 from factory - datecode 1B (common)
CECH-25xx (JTP-001) with 3.56 from factory - datecode 1B (common)		 E9 60 0E 92 2F5F0 2F 5B 2F 5B (RLOD+)poweroff @ downgrade 355
(3.56+ + spkg fix + signed 3.55 priv : should work)
Patch + noFSM = OK		 3.56
3.56
3.56
0B
0B
0C		 CECH-25xx (JSD-001) with 3.60 from factory - datecode 1B
CECH-25xx (JTP-001) with 3.60 from factory - datecode [N.A.]
CECH-30xx (KTE-001) with 3.65 from factory - datecode [N.A.]		 F9 20 0F 8E 2FFF0 2F FB 2F FB "metldr.2"
(RLOD+)poweroff @ downgrade 3.55
(RLOD+)poweroff @ Patch + noFSM		 3.60
3.60
3.60
0C CECH-30xx (KTE-001) with ? from factory - datecode [?] F9 B0 0F 97 30070 30 03 30 03 "metldr.2"
(RLOD+)poweroff @ downgrade 3.55
(RLOD+)poweroff @ Patch + noFSM		 ?
0C CECH-30xx (KTE-001) with 3.72 from factory - datecode [1C] F9 B0 0F 97 300F0 30 0B 30 0B "metldr.2"
(RLOD+)poweroff @ downgrade 3.55
(RLOD+)poweroff @ Patch + noFSM		 3.72
0D
0D
2C		 CECH-40xx (MSX-001)
CECH-40xx (MPX-001)
CECH-40xx (MSX-001) '12GB'		 F9 B0 0F 97 301F0 30 1B 30 1B "metldr.2"
(RLOD+)poweroff @ downgrade 3.55
(RLOD+)poweroff @ Patch + noFSM		 4.20
?
4.22
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