Editing CXD9208GP

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Line 19: Line 19:
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
|-
|-
| data-sort-value="A04" | A4 || {{cellcolors|#8f8}} SIF_WRAC || SIF_WRAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B23 (write ?)
| data-sort-value="A04" | A4 || {{cellcolors|#8f8}} SIF_WRAC || SIF_WRAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B23
|-
|-
| data-sort-value="A05" | A5 || {{cellcolors|#8f8}} SIF_DACK || SIF_DACK_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A25
| data-sort-value="A05" | A5 || {{cellcolors|#8f8}} SIF_DACK || SIF_DACK_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A25
Line 25: Line 25:
| data-sort-value="A06" | A6 || {{cellcolors|#8f8}} SIF_DREQ0 || SIF_DREQ0_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B24
| data-sort-value="A06" | A6 || {{cellcolors|#8f8}} SIF_DREQ0 || SIF_DREQ0_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B24
|-
|-
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23 (read ?)
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23
|-
|-
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#afa}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#8f8}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
|-
|-
| data-sort-value="A09" | A9 || data-sort-value="SIF_AD07" {{cellcolors|#afa}} SIF_AD7 || data-sort-value="SIF_BC_AD07" | SIF_BC_AD7 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C18
| data-sort-value="A09" | A9 || data-sort-value="SIF_AD07" {{cellcolors|#8f8}} SIF_AD7 || data-sort-value="SIF_BC_AD07" | SIF_BC_AD7 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C18
|-
|-
| data-sort-value="A10" | A10 || data-sort-value="SIF_AD09" {{cellcolors|#afa}} SIF_AD9 || data-sort-value="SIF_BC_AD09" | SIF_BC_AD9 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B18
| data-sort-value="A10" | A10 || data-sort-value="SIF_AD09" {{cellcolors|#8f8}} SIF_AD9 || data-sort-value="SIF_BC_AD09" | SIF_BC_AD9 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B18
|-
|-
| data-sort-value="A11" | A11 || {{cellcolors|#afa}} SIF_AD18 || SIF_BC_AD18 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A12
| data-sort-value="A11" | A11 || {{cellcolors|#8f8}} SIF_AD18 || SIF_BC_AD18 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A12
|-
|-
| data-sort-value="A12" | A12 || {{cellcolors|#afa}} SIF_AD21 || SIF_BC_AD21 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C11
| data-sort-value="A12" | A12 || {{cellcolors|#8f8}} SIF_AD21 || SIF_BC_AD21 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C11
|-
|-
| data-sort-value="A13" | A13 || {{cellcolors|#afa}} SIF_AD29 || SIF_BC_AD29 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B9
| data-sort-value="A13" | A13 || {{cellcolors|#8f8}} SIF_AD29 || SIF_BC_AD29 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B9
|-
|-
| data-sort-value="A14" | A14 || data-sort-value="SIF_AD06" {{cellcolors|#afa}} SIF_AD6 || data-sort-value="SIF_BC_AD06" | SIF_BC_AD6 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A18
| data-sort-value="A14" | A14 || data-sort-value="SIF_AD06" {{cellcolors|#8f8}} SIF_AD6 || data-sort-value="SIF_BC_AD06" | SIF_BC_AD6 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A18
|-
|-
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
Line 51: Line 51:
| data-sort-value="B04" | B4 || {{cellcolors|#8f8}} SIF_SINT || SINT_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C21
| data-sort-value="B04" | B4 || {{cellcolors|#8f8}} SIF_SINT || SINT_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C21
|-
|-
| data-sort-value="B05" | B5 || {{cellcolors|#6b6}} SIF_BE3 || SIF_BE3_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C24
| data-sort-value="B05" | B5 || {{cellcolors|#8f8}} SIF_BE3 || SIF_BE3_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C24
|-
|-
| data-sort-value="B06" | B6 || {{cellcolors|#8f8}} SIF_DREQ1 || SIF_DREQ1_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A24
| data-sort-value="B06" | B6 || {{cellcolors|#8f8}} SIF_DREQ1 || SIF_DREQ1_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A24
Line 57: Line 57:
| data-sort-value="B07" | B7 || {{cellcolors|#8f8}} SIF_RDY || SIF_RDY_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A22
| data-sort-value="B07" | B7 || {{cellcolors|#8f8}} SIF_RDY || SIF_RDY_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A22
|-
|-
| data-sort-value="B08" | B8 || {{cellcolors|#6b6}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
| data-sort-value="B08" | B8 || {{cellcolors|#8f8}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
|-
|-
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#afa}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#8f8}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
|-
|-
| data-sort-value="B10" | B10 || data-sort-value="SIF_AD03" {{cellcolors|#afa}} SIF_AD3 || data-sort-value="SIF_BC_AD03" | SIF_BC_AD3 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C19
| data-sort-value="B10" | B10 || data-sort-value="SIF_AD03" {{cellcolors|#8f8}} SIF_AD3 || data-sort-value="SIF_BC_AD03" | SIF_BC_AD3 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C19
|-
|-
| data-sort-value="B11" | B11 || {{cellcolors|#afa}} SIF_AD20 || SIF_BC_AD20 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A11
| data-sort-value="B11" | B11 || {{cellcolors|#8f8}} SIF_AD20 || SIF_BC_AD20 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A11
|-
|-
| data-sort-value="B12" | B12 || {{cellcolors|#afa}} SIF_AD30 || SIF_BC_AD30 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C9
| data-sort-value="B12" | B12 || {{cellcolors|#8f8}} SIF_AD30 || SIF_BC_AD30 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C9
|-
|-
| data-sort-value="B13" | B13 || {{cellcolors|#afa}} SIF_AD26 || SIF_BC_AD26 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A9
| data-sort-value="B13" | B13 || {{cellcolors|#8f8}} SIF_AD26 || SIF_BC_AD26 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A9
|-
|-
| data-sort-value="B14" | B14 || {{cellcolors|#afa}} SIF_AD11 || SIF_BC_AD11 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C15
| data-sort-value="B14" | B14 || {{cellcolors|#8f8}} SIF_AD11 || SIF_BC_AD11 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C15
|-
|-
| data-sort-value="B99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="B99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="C01" | C1 || {{cellcolors|#bbf}} PCI_AD30 || BC_PCI_AD30 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU31
| data-sort-value="C01" | C1 || {{cellcolors|#99f}} PCI_AD30 || BC_PCI_AD30 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU31
|-
|-
| data-sort-value="C02" | C2 || {{cellcolors|#bbf}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
| data-sort-value="C02" | C2 || {{cellcolors|#99f}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
|-
|-
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
Line 83: Line 83:
| data-sort-value="C05" | C5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C05" | C5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="C06" | C6 || {{cellcolors|#6b6}} SIF_BE0 || SIF_BE0_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B22
| data-sort-value="C06" | C6 || {{cellcolors|#8f8}} SIF_BE0 || SIF_BE0_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B22
|-
|-
| data-sort-value="C07" | C7 || {{cellcolors|#6b6}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
| data-sort-value="C07" | C7 || {{cellcolors|#8f8}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
|-
|-
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#afa}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#8f8}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
|-
|-
| data-sort-value="C09" | C9 || data-sort-value="SIF_AD00" {{cellcolors|#afa}} SIF_AD0 || data-sort-value="SIF_BC_AD00" | SIF_BC_AD0 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B19
| data-sort-value="C09" | C9 || data-sort-value="SIF_AD00" {{cellcolors|#8f8}} SIF_AD0 || data-sort-value="SIF_BC_AD00" | SIF_BC_AD0 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B19
|-
|-
| data-sort-value="C10" | C10 || {{cellcolors|#afa}} SIF_AD28 || SIF_BC_AD28 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B12
| data-sort-value="C10" | C10 || {{cellcolors|#8f8}} SIF_AD28 || SIF_BC_AD28 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B12
|-
|-
| data-sort-value="C11" | C11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C11" | C11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 97: Line 97:
| data-sort-value="C12" | C12 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C12" | C12 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="C13" | C13 || {{cellcolors|#afa}} SIF_AD31 || SIF_BC_AD31 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A8
| data-sort-value="C13" | C13 || {{cellcolors|#8f8}} SIF_AD31 || SIF_BC_AD31 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A8
|-
|-
| data-sort-value="C14" | C14 || {{cellcolors|#afa}} SIF_AD15 || SIF_BC_AD15 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B15
| data-sort-value="C14" | C14 || {{cellcolors|#8f8}} SIF_AD15 || SIF_BC_AD15 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B15
|-
|-
| data-sort-value="C99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="C99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="D01" | D1 || {{cellcolors|#bbf}} PCI_AD26 || BC_PCI_AD26 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU30
| data-sort-value="D01" | D1 || {{cellcolors|#99f}} PCI_AD26 || BC_PCI_AD26 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU30
|-
|-
| data-sort-value="D02" | D2 || {{cellcolors|#bbf}} PCI_AD28 || BC_PCI_AD28 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW31
| data-sort-value="D02" | D2 || {{cellcolors|#99f}} PCI_AD28 || BC_PCI_AD28 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW31
|-
|-
| data-sort-value="D03" | D3 || {{cellcolors|#bbf}} PCI_AD31 || BC_PCI_AD31 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT31
| data-sort-value="D03" | D3 || {{cellcolors|#99f}} PCI_AD31 || BC_PCI_AD31 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT31
|-
|-
| data-sort-value="D04" | D4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="D04" | D4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 125: Line 125:
| data-sort-value="D11" | D11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="D11" | D11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
|-
|-
| data-sort-value="D12" | D12 || {{cellcolors|#afa}} SIF_AD10 || SIF_BC_AD10 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B16
| data-sort-value="D12" | D12 || {{cellcolors|#8f8}} SIF_AD10 || SIF_BC_AD10 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B16
|-
|-
| data-sort-value="D13" | D13 || data-sort-value="SIF_AD05" {{cellcolors|#afa}} SIF_AD5 || data-sort-value="SIF_BC_AD05" | SIF_BC_AD5 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A17
| data-sort-value="D13" | D13 || data-sort-value="SIF_AD05" {{cellcolors|#8f8}} SIF_AD5 || data-sort-value="SIF_BC_AD05" | SIF_BC_AD5 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A17
|-
|-
| data-sort-value="D14" | D14 || {{cellcolors|#afa}} SIF_AD14 || SIF_BC_AD14 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B14
| data-sort-value="D14" | D14 || {{cellcolors|#8f8}} SIF_AD14 || SIF_BC_AD14 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B14
|-
|-
| data-sort-value="D99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="D99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="E01" | E1 || {{cellcolors|#bbf}} PCI_AD25 || BC_PCI_AD25 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT29
| data-sort-value="E01" | E1 || {{cellcolors|#99f}} PCI_AD25 || BC_PCI_AD25 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT29
|-
|-
| data-sort-value="E02" | E2 || {{cellcolors|#bbf}} PCI_AD27 || BC_PCI_AD27 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT30
| data-sort-value="E02" | E2 || {{cellcolors|#99f}} PCI_AD27 || BC_PCI_AD27 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT30
|-
|-
| data-sort-value="E03" | E3 || {{cellcolors|#bbf}} PCI_AD24 || BC_PCI_AD24 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU29
| data-sort-value="E03" | E3 || {{cellcolors|#99f}} PCI_AD24 || BC_PCI_AD24 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU29
|-
|-
| data-sort-value="E04" | E4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E04" | E4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
Line 157: Line 157:
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#afa}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#8f8}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
|-
|-
| data-sort-value="E14" | E14 || {{cellcolors|#afa}} SIF_AD13 || SIF_BC_AD13 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C14
| data-sort-value="E14" | E14 || {{cellcolors|#8f8}} SIF_AD13 || SIF_BC_AD13 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C14
|-
|-
| data-sort-value="E99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="E99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="F01" | F1 || {{cellcolors|#bbf}} PCI_AD20 || BC_PCI_AD20 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU28
| data-sort-value="F01" | F1 || {{cellcolors|#99f}} PCI_AD20 || BC_PCI_AD20 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU28
|-
|-
| data-sort-value="F02" | F2 || {{cellcolors|#bbf}} PCI_AD22 || BC_PCI_AD22 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW29
| data-sort-value="F02" | F2 || {{cellcolors|#99f}} PCI_AD22 || BC_PCI_AD22 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW29
|-
|-
| data-sort-value="F03" | F3 || {{cellcolors|#bbf}} PCI_AD18 || BC_PCI_AD18 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU27
| data-sort-value="F03" | F3 || {{cellcolors|#99f}} PCI_AD18 || BC_PCI_AD18 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU27
|-
|-
| data-sort-value="F04" | F4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="F04" | F4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 187: Line 187:
| data-sort-value="F12" | F12 || {{cellcolors|#eee|#888}} GPIO15_0 || CL7306 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F12" | F12 || {{cellcolors|#eee|#888}} GPIO15_0 || CL7306 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="F13" | F13 || {{cellcolors|#afa}} SIF_AD12 || SIF_BC_AD12 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A15
| data-sort-value="F13" | F13 || {{cellcolors|#8f8}} SIF_AD12 || SIF_BC_AD12 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A15
|-
|-
| data-sort-value="F14" | F14 || {{cellcolors|#afa}} SIF_AD24 || SIF_BC_AD24 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B11
| data-sort-value="F14" | F14 || {{cellcolors|#8f8}} SIF_AD24 || SIF_BC_AD24 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B11
|-
|-
| data-sort-value="F99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="F99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="G01" | G1 || {{cellcolors|#bbf}} PCI_AD21 || BC_PCI_AD21 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT28
| data-sort-value="G01" | G1 || {{cellcolors|#99f}} PCI_AD21 || BC_PCI_AD21 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT28
|-
|-
| data-sort-value="G02" | G2 || {{cellcolors|#bbf}} PCI_AD23 || BC_PCI_AD23 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV29
| data-sort-value="G02" | G2 || {{cellcolors|#99f}} PCI_AD23 || BC_PCI_AD23 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV29
|-
|-
| data-sort-value="G03" | G3 || {{cellcolors|#99f}} PCI_IDSEL || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="G03" | G3 || {{cellcolors|#99f}} PCI_IDSEL || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
Line 217: Line 217:
| data-sort-value="G12" | G12 || {{cellcolors|#eee|#888}} GPIO15_1 || CL7311 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="G12" | G12 || {{cellcolors|#eee|#888}} GPIO15_1 || CL7311 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="G13" | G13 || {{cellcolors|#afa}} SIF_AD16 || SIF_BC_AD16 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A14
| data-sort-value="G13" | G13 || {{cellcolors|#8f8}} SIF_AD16 || SIF_BC_AD16 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A14
|-
|-
| data-sort-value="G14" | G14 || {{cellcolors|#afa}} SIF_AD23 || SIF_BC_AD23 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A10
| data-sort-value="G14" | G14 || {{cellcolors|#8f8}} SIF_AD23 || SIF_BC_AD23 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A10
|-
|-
| data-sort-value="G99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="G99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="H01" | H1 || {{cellcolors|#bbf}} PCI_AD15 || BC_PCI_AD15 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT23
| data-sort-value="H01" | H1 || {{cellcolors|#99f}} PCI_AD15 || BC_PCI_AD15 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT23
|-
|-
| data-sort-value="H02" | H2 || {{cellcolors|#bbf}} PCI_AD16 || BC_PCI_AD16 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW27
| data-sort-value="H02" | H2 || {{cellcolors|#99f}} PCI_AD16 || BC_PCI_AD16 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW27
|-
|-
| data-sort-value="H03" | H3 || {{cellcolors|#bbf}} PCI_AD19 || BC_PCI_AD19 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT27
| data-sort-value="H03" | H3 || {{cellcolors|#99f}} PCI_AD19 || BC_PCI_AD19 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT27
|-
|-
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 247: Line 247:
| data-sort-value="H12" | H12 || {{cellcolors|#eee|#888}} GPIO15_2 || CL7305 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="H12" | H12 || {{cellcolors|#eee|#888}} GPIO15_2 || CL7305 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="H13" | H13 || {{cellcolors|#afa}} SIF_AD22 || SIF_BC_AD22 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C13
| data-sort-value="H13" | H13 || {{cellcolors|#8f8}} SIF_AD22 || SIF_BC_AD22 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C13
|-
|-
| data-sort-value="H14" | H14 || {{cellcolors|#afa}} SIF_AD25 || SIF_BC_AD25 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B10
| data-sort-value="H14" | H14 || {{cellcolors|#8f8}} SIF_AD25 || SIF_BC_AD25 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B10
|-
|-
| data-sort-value="H99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="H99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="J01" | J1 || {{cellcolors|#bbf}} PCI_AD14 || BC_PCI_AD14 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU23
| data-sort-value="J01" | J1 || {{cellcolors|#99f}} PCI_AD14 || BC_PCI_AD14 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU23
|-
|-
| data-sort-value="J02" | J2 || {{cellcolors|#bbf}} PCI_AD17 || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="J02" | J2 || {{cellcolors|#99f}} PCI_AD17 || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
|-
|-
| data-sort-value="J03" | J3 || data-sort-value="PCI_AD06" {{cellcolors|#bbf}} PCI_AD6 || data-sort-value="BC_PCI_AD06" | BC_PCI_AD6 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW21
| data-sort-value="J03" | J3 || data-sort-value="PCI_AD06" {{cellcolors|#99f}} PCI_AD6 || data-sort-value="BC_PCI_AD06" | BC_PCI_AD6 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW21
|-
|-
| data-sort-value="J04" | J4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="J04" | J4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 277: Line 277:
| data-sort-value="J12" | J12 || {{cellcolors|#eee|#888}} GPIO33_0 || CL7310 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="J12" | J12 || {{cellcolors|#eee|#888}} GPIO33_0 || CL7310 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="J13" | J13 || {{cellcolors|#afa}} SIF_AD19 || SIF_BC_AD19 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B13
| data-sort-value="J13" | J13 || {{cellcolors|#8f8}} SIF_AD19 || SIF_BC_AD19 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B13
|-
|-
| data-sort-value="J14" | J14 || {{cellcolors|#afa}} SIF_AD27 || SIF_BC_AD27 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C10
| data-sort-value="J14" | J14 || {{cellcolors|#8f8}} SIF_AD27 || SIF_BC_AD27 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C10
|-
|-
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="K01" | K1 || data-sort-value="PCI_AD09" {{cellcolors|#bbf}} PCI_AD9 || data-sort-value="BC_PCI_AD09" | BC_PCI_AD9 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT21
| data-sort-value="K01" | K1 || data-sort-value="PCI_AD09" {{cellcolors|#99f}} PCI_AD9 || data-sort-value="BC_PCI_AD09" | BC_PCI_AD9 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT21
|-
|-
| data-sort-value="K02" | K2 || {{cellcolors|#bbf}} PCI_AD11 || BC_PCI_AD11 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT22
| data-sort-value="K02" | K2 || {{cellcolors|#99f}} PCI_AD11 || BC_PCI_AD11 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT22
|-
|-
| data-sort-value="K03" | K3 || {{cellcolors|#bbf}} PCI_AD10 || BC_PCI_AD10 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU22
| data-sort-value="K03" | K3 || {{cellcolors|#99f}} PCI_AD10 || BC_PCI_AD10 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU22
|-
|-
| data-sort-value="K04" | K4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K04" | K4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 307: Line 307:
| data-sort-value="K12" | K12 || {{cellcolors|#eee|#888}} GPIO33_1 || CL7304 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="K12" | K12 || {{cellcolors|#eee|#888}} GPIO33_1 || CL7304 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="K13" | K13 || {{cellcolors|#afa}} SIF_AD17 || SIF_BC_AD17 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A13
| data-sort-value="K13" | K13 || {{cellcolors|#8f8}} SIF_AD17 || SIF_BC_AD17 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A13
|-
|-
| data-sort-value="K14" | K14 || {{cellcolors|#8f8}} SIF_BREQ || BREQ_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A7
| data-sort-value="K14" | K14 || {{cellcolors|#8f8}} SIF_BREQ || BREQ_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A7
Line 313: Line 313:
| data-sort-value="K99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="K99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="L01" | L1 || data-sort-value="PCI_AD03" {{cellcolors|#bbf}} PCI_AD3 || data-sort-value="BC_PCI_AD03" | BC_PCI_AD3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT19
| data-sort-value="L01" | L1 || data-sort-value="PCI_AD03" {{cellcolors|#99f}} PCI_AD3 || data-sort-value="BC_PCI_AD03" | BC_PCI_AD3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT19
|-
|-
| data-sort-value="L02" | L2 || data-sort-value="PCI_AD07" {{cellcolors|#bbf}} PCI_AD7 || data-sort-value="BC_PCI_AD07" | BC_PCI_AD7 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV21
| data-sort-value="L02" | L2 || data-sort-value="PCI_AD07" {{cellcolors|#99f}} PCI_AD7 || data-sort-value="BC_PCI_AD07" | BC_PCI_AD7 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV21
|-
|-
| data-sort-value="L03" | L3 || {{cellcolors|#bbf}} PCI_AD13 || BC_PCI_AD13 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV23
| data-sort-value="L03" | L3 || {{cellcolors|#99f}} PCI_AD13 || BC_PCI_AD13 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV23
|-
|-
| data-sort-value="L04" | L4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="L04" | L4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 343: Line 343:
| data-sort-value="L99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="L99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="M01" | M1 || data-sort-value="PCI_AD04" {{cellcolors|#bbf}} PCI_AD4 || data-sort-value="BC_PCI_AD04" | BC_PCI_AD4 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU20
| data-sort-value="M01" | M1 || data-sort-value="PCI_AD04" {{cellcolors|#99f}} PCI_AD4 || data-sort-value="BC_PCI_AD04" | BC_PCI_AD4 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU20
|-
|-
| data-sort-value="M02" | M2 || data-sort-value="PCI_AD02" {{cellcolors|#bbf}} PCI_AD2 || data-sort-value="BC_PCI_AD02" | BC_PCI_AD2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU19
| data-sort-value="M02" | M2 || data-sort-value="PCI_AD02" {{cellcolors|#99f}} PCI_AD2 || data-sort-value="BC_PCI_AD02" | BC_PCI_AD2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU19
|-
|-
| data-sort-value="M03" | M3 || data-sort-value="PCI_AD01" {{cellcolors|#bbf}} PCI_AD1 || data-sort-value="BC_PCI_AD01" | BC_PCI_AD1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV19
| data-sort-value="M03" | M3 || data-sort-value="PCI_AD01" {{cellcolors|#99f}} PCI_AD1 || data-sort-value="BC_PCI_AD01" | BC_PCI_AD1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV19
|-
|-
| data-sort-value="M04" | M4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="M04" | M4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
Line 357: Line 357:
| data-sort-value="M07" | M7 || {{cellcolors|#99f}} PCI_TRDY || BC_PCI_TRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT25
| data-sort-value="M07" | M7 || {{cellcolors|#99f}} PCI_TRDY || BC_PCI_TRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT25
|-
|-
| data-sort-value="M08" | M8 || {{cellcolors|#77f}} PCI_CBE0 || BC_PCI_CBE0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP19
| data-sort-value="M08" | M8 || {{cellcolors|#99f}} PCI_CBE0 || BC_PCI_CBE0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP19
|-
|-
| data-sort-value="M09" | M9 || {{cellcolors|#99f}} PCI_FRAME || BC_PCI_FRAME || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT26
| data-sort-value="M09" | M9 || {{cellcolors|#99f}} PCI_FRAME || BC_PCI_FRAME || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT26
Line 373: Line 373:
| data-sort-value="M99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="M99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="N01" | N1 || data-sort-value="PCI_AD08" {{cellcolors|#bbf}} PCI_AD8 || data-sort-value="BC_PCI_AD08" | BC_PCI_AD8 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU21
| data-sort-value="N01" | N1 || data-sort-value="PCI_AD08" {{cellcolors|#99f}} PCI_AD8 || data-sort-value="BC_PCI_AD08" | BC_PCI_AD8 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU21
|-
|-
| data-sort-value="N02" | N2 || data-sort-value="PCI_AD05" {{cellcolors|#bbf}} PCI_AD5 || data-sort-value="BC_PCI_AD05" | BC_PCI_AD5 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT20
| data-sort-value="N02" | N2 || data-sort-value="PCI_AD05" {{cellcolors|#99f}} PCI_AD5 || data-sort-value="BC_PCI_AD05" | BC_PCI_AD5 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT20
|-
|-
| data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
|-
|-
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#bbf}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#99f}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
|-
|-
| data-sort-value="N05" | N5 || {{cellcolors|#99f|#a00}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24 (system error)
| data-sort-value="N05" | N5 || {{cellcolors|#99f}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24
|-
|-
| data-sort-value="N06" | N6 || {{cellcolors|#99f}} PCI_DEVSEL || BC_PCI_DEVSEL || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU25
| data-sort-value="N06" | N6 || {{cellcolors|#99f}} PCI_DEVSEL || BC_PCI_DEVSEL || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU25
|-
|-
| data-sort-value="N07" | N7 || {{cellcolors|#77f}} PCI_CBE2 || BC_PCI_CBE2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP20
| data-sort-value="N07" | N7 || {{cellcolors|#99f}} PCI_CBE2 || BC_PCI_CBE2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP20
|-
|-
| data-sort-value="N08" | N8 || {{cellcolors|#99f}} PCI_GNT || BC_PCI_GNT1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN24
| data-sort-value="N08" | N8 || {{cellcolors|#99f}} PCI_GNT || BC_PCI_GNT1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN24
Line 403: Line 403:
| data-sort-value="N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="P01" | P1 || {{cellcolors|#bbf}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
| data-sort-value="P01" | P1 || {{cellcolors|#99f}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
|-
|-
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
Line 409: Line 409:
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
|-
|-
| data-sort-value="P04" | P4 || {{cellcolors|#77f}} PCI_CBE1 || BC_PCI_CBE1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN19
| data-sort-value="P04" | P4 || {{cellcolors|#99f}} PCI_CBE1 || BC_PCI_CBE1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN19
|-
|-
| data-sort-value="P05" | P5 || {{cellcolors|#99f|#a00}} PCI_PERR || BC_PCI_PERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW25 (parity error)
| data-sort-value="P05" | P5 || {{cellcolors|#99f}} PCI_PERR || BC_PCI_PERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW25
|-
|-
| data-sort-value="P06" | P6 || {{cellcolors|#99f}} PCI_IRDY || BC_PCI_IRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU26
| data-sort-value="P06" | P6 || {{cellcolors|#99f}} PCI_IRDY || BC_PCI_IRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU26
|-
|-
| data-sort-value="P07" | P7 || {{cellcolors|#77f}} PCI_CBE3 || BC_PCI_CBE3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN20
| data-sort-value="P07" | P7 || {{cellcolors|#99f}} PCI_CBE3 || BC_PCI_CBE3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN20
|-
|-
| data-sort-value="P08" | P8 || {{cellcolors|#99f}} PCI_REQ || BC_PCI_REQ1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN22
| data-sort-value="P08" | P8 || {{cellcolors|#99f}} PCI_REQ || BC_PCI_REQ1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN22
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