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<div style="float:right">[[File:PCI pads - as seen on COK-002.jpg|200px|thumb|left|PCI pads - as seen on COK-002<br>note: Two circular pads in the bottom right corner are for southbridge serial]]</div>
[[Category:Hardware]]
<div style="float:right">[[File:TMU-520_1-871-645-11_A_Detail_9_(CP_Con.).jpg|200px|thumb|left|Communication Processor (PCI) connector beneath the PCIe x4 connector on a TMU-520]]</div>
<div style="float:right">[[File:PCI pads - as seen on COK-002.jpg|200px|thumb|left|File:PCI pads - as seen on COK-002<br />note: Two circular pads in the bottom right corner are for southbridge serial]]</div>
<div style="float:right">[[File:PCI connector JSD-001 SB and SC UART.jpg|200px|thumb|left|PCI connector JSD-001 SB and SC UART]]</div>


== PCI ==
== PCI ==
Bus, resembling Conventional PCI 2.3, directly connected to [[South Bridge]], with 80 exposed pads
Bus, resembling Conventional PCI 2.3, directly connected to [[South Bridge]], with 80 exposed pads
Activated by setting offset 0x48C02 in [[SC EEPROM]] to 0x00 or 0x03:
* 0x00 is for IFB (InterFace Board, used by [[SKU_Models_Nonretail#Nonretail_prototypes_.28CEB.29|CEB]])
* 0x03 is for [[Communication Processor]] (PIF5, used by [[SKU_Models_Nonretail#Reference_tool_prototypes_.28DEHR.29|DEH-R10XX]] and [[DECR-1000]])
** Does also have support for '''all''' ''retail platforms'' (e.g. [[COK-00x#COK-001|COK-001]], [[VER-00x#VER-001|VER-001]] or [[RTX-00x#RTX-001|RTX-001]])
Supported devices:
{| class="wikitable sortable"
|-
! Device ID !! Device "Name" !! Firmware
|-
| 104D8183 || Sony IFB ATHENS Board Revision 0x1 || [[010.???]] to {{latestPS3}}
|-
| 104D81FF || Sony PIF5 [[TMR-520|TMR]] Board Revision 0x101 || [[0.6.0.004.r010|060.004]] to {{latestPS3}}
|-
| 104D8200 || Sony DVE (RSX Tracing) FPGA || [[0.8.2.006.r010|082.006]] to {{latestPS3}}
|-
| 104D820E || Sony [[CXD9208GP]] PS2 emulation subsystem adapter || [[0.8.2.006.r010|082.006]] to {{latestPS3}}
|-
| 80861076 || Intel 82541PI Gigabit Ethernet Controller || [[010.???]] to {{latestPS3}}
|-
|}


Major differences from PCI standard:
Major differences from PCI standard:
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* no support for optional JTAG signals, nor for the 64-bit PCI extension defined in the PCI Local Bus Specification
* no support for optional JTAG signals, nor for the 64-bit PCI extension defined in the PCI Local Bus Specification


=== 70/80 pin miniPCI pad layout ===
=== 80 pin miniPCI pad layout ===
CN3208 80P on [[CECHAxx]]/[[CECHBxx]] [[COK-00x#COK-001|COK-001]], [[CECHCxx]]/[[CECHExx]] [[COK-00x#COK-002|COK-002(W)]], [[CECH-20xx]] [[DYN-00x#DYN-001|DYN-001]] and '''all''' [[Motherboard_Revisions#DYN-001|later models]]
CN3208 80P on [[CECHAxx]]/[[CECHBxx]] [[COK-00x#COK-001|COK-001]] and [[CECHCxx]]/[[CECHExx]] [[COK-00x#COK-002|COK-002]]


CN3208 70P on [[CECHGxx]] [[SEM-00x#SEM-001|SEM-001]], [[CECHHxx]] [[DIA-00x#DIA-001|DIA-001]], [[CECHJxx]]/[[CECHKxx]] [[DIA-00x#DIA-002|DIA-002]] and [[CECHLxx]]/[[CECHMxx]]/[[CECHPxx]]/[[CECHQxx]] [[VER-00x#VER-001|VER-001]]
CN3208 70P on [[CECHGxx]] [[SEM-00x|SEM-001]]


{| class="wikitable sortable"
{| class="wikitable sortable"
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|}
|}


==== [[South Bridge]] serial ====
=== [[South Bridge]] serial ===
{| class="wikitable sortable"
{| class="wikitable sortable"
|-
|-
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|}
|}


=== 160 pin pad layout ===
CN4301 160P on [[DECR-1000]] [[TMU-520]] (only partly used for PCI)<br />
'''TODO'''
{{Wikify}}


{{Console}}


{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude>
[[Category:PCI]]
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