Editing Template:CELL pad layout 90nm

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| data-sort-value="0A01" | A1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0A01" | A1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0A02" | A2 || Y0_DQ1N_5 || Y0_XDR0_DQN10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0A02" | A2 || Y0_DQ1N_5 || Y0_XDR0_DQN10 || {{pino}} ||  
|-
|-
| data-sort-value="0A03" | A3 || Y0_DQ1N_2 || data-sort-value="Y0_XDR0_DQN06" | Y0_XDR0_DQN6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0A03" | A3 || Y0_DQ1N_2 || data-sort-value="Y0_XDR0_DQN06" | Y0_XDR0_DQN6 || {{pino}} ||  
|-
|-
| data-sort-value="0A04" | A4 || Y0_DQ0N_6 || Y0_XDR0_DQN14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0A04" | A4 || Y0_DQ0N_6 || Y0_XDR0_DQN14 || {{pino}} ||  
|-
|-
| data-sort-value="0A05" | A5 || Y0_DQ0N_4 || data-sort-value="Y0_XDR0_DQN02" | Y0_XDR0_DQN2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0A05" | A5 || Y0_DQ0N_4 || data-sort-value="Y0_XDR0_DQN02" | Y0_XDR0_DQN2 || {{pino}} ||  
|-
|-
| data-sort-value="0A06" | A6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0A06" | A6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 28: Line 28:
| data-sort-value="0A07" | A7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0A07" | A7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0A08" | A8 || Y0_DQ0N_1 || Y0_XDR1_DQN14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0A08" | A8 || Y0_DQ0N_1 || Y0_XDR1_DQN14 || {{pino}} ||  
|-
|-
| data-sort-value="0A09" | A9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0A09" | A9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
Line 100: Line 100:
| data-sort-value="0B01" | B1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0B01" | B1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0B02" | B2 || Y0_DQ1_5 || Y0_XDR0_DQ10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0B02" | B2 || Y0_DQ1_5 || Y0_XDR0_DQ10 || {{pino}} ||  
|-
|-
| data-sort-value="0B03" | B3 || Y0_DQ1_2 || data-sort-value="Y0_XDR0_DQ06" | Y0_XDR0_DQ6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0B03" | B3 || Y0_DQ1_2 || data-sort-value="Y0_XDR0_DQ06" | Y0_XDR0_DQ6 || {{pino}} ||  
|-
|-
| data-sort-value="0B04" | B4 || Y0_DQ0_6 || Y0_XDR0_DQ14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0B04" | B4 || Y0_DQ0_6 || Y0_XDR0_DQ14 || {{pino}} ||  
|-
|-
| data-sort-value="0B05" | B5 || Y0_DQ0_4 || data-sort-value="Y0_XDR0_DQ02" | Y0_XDR0_DQ2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0B05" | B5 || Y0_DQ0_4 || data-sort-value="Y0_XDR0_DQ02" | Y0_XDR0_DQ2 || {{pino}} ||  
|-
|-
| data-sort-value="0B06" | B6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0B06" | B6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 112: Line 112:
| data-sort-value="0B07" | B7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0B07" | B7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0B08" | B8 || Y0_DQ0_1 || Y0_XDR1_DQ14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0B08" | B8 || Y0_DQ0_1 || Y0_XDR1_DQ14 || {{pino}} ||  
|-
|-
| data-sort-value="0B09" | B9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0B09" | B9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
Line 184: Line 184:
| data-sort-value="0C01" | C1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0C01" | C1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0C02" | C2 || Y0_DQ1N_6 || data-sort-value="Y0_XDR0_DQN00" | Y0_XDR0_DQN0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C02" | C2 || Y0_DQ1N_6 || data-sort-value="Y0_XDR0_DQN00" | Y0_XDR0_DQN0 || {{pino}} ||  
|-
|-
| data-sort-value="0C03" | C3 || Y0_DQ1N_4 || Y0_XDR0_DQN12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C03" | C3 || Y0_DQ1N_4 || Y0_XDR0_DQN12 || {{pino}} ||  
|-
|-
| data-sort-value="0C04" | C4 || Y0_DQ0N_0 || data-sort-value="Y0_XDR0_DQN04" | Y0_XDR0_DQN4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C04" | C4 || Y0_DQ0N_0 || data-sort-value="Y0_XDR0_DQN04" | Y0_XDR0_DQN4 || {{pino}} ||  
|-
|-
| data-sort-value="0C05" | C5 || Y0_DQ0N_5 || data-sort-value="Y0_XDR0_DQN08" | Y0_XDR0_DQN8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C05" | C5 || Y0_DQ0N_5 || data-sort-value="Y0_XDR0_DQN08" | Y0_XDR0_DQN8 || {{pino}} ||  
|-
|-
| data-sort-value="0C06" | C6 || Y0_DQ1N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="0C06" | C6 || Y0_DQ1N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
|-
|-
| data-sort-value="0C07" | C7 || Y0_DQ1N_3 || Y0_XDR1_DQN10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C07" | C7 || Y0_DQ1N_3 || Y0_XDR1_DQN10 || {{pino}} ||  
|-
|-
| data-sort-value="0C08" | C8 || Y0_DQ1N_1 || data-sort-value="Y0_XDR1_DQN06" | Y0_XDR1_DQN6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C08" | C8 || Y0_DQ1N_1 || data-sort-value="Y0_XDR1_DQN06" | Y0_XDR1_DQN6 || {{pino}} ||  
|-
|-
| data-sort-value="0C09" | C9 || Y0_DQ0N_3 || data-sort-value="Y0_XDR1_DQN02" | Y0_XDR1_DQN2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0C09" | C9 || Y0_DQ0N_3 || data-sort-value="Y0_XDR1_DQN02" | Y0_XDR1_DQN2 || {{pino}} ||  
|-
|-
| data-sort-value="0C10" | C10 || Y0_DQ0N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="0C10" | C10 || Y0_DQ0N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
Line 268: Line 268:
| data-sort-value="0D01" | D1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0D01" | D1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0D02" | D2 || Y0_DQ1_6 || data-sort-value="Y0_XDR0_DQ00" | Y0_XDR0_DQ0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D02" | D2 || Y0_DQ1_6 || data-sort-value="Y0_XDR0_DQ00" | Y0_XDR0_DQ0 || {{pino}} ||  
|-
|-
| data-sort-value="0D03" | D3 || Y0_DQ1_4 || Y0_XDR0_DQ12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D03" | D3 || Y0_DQ1_4 || Y0_XDR0_DQ12 || {{pino}} ||  
|-
|-
| data-sort-value="0D04" | D4 || Y0_DQ0_0 || data-sort-value="Y0_XDR0_DQ04" | Y0_XDR0_DQ4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D04" | D4 || Y0_DQ0_0 || data-sort-value="Y0_XDR0_DQ04" | Y0_XDR0_DQ4 || {{pino}} ||  
|-
|-
| data-sort-value="0D05" | D5 || Y0_DQ0_5 || data-sort-value="Y0_XDR0_DQ08" | Y0_XDR0_DQ8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D05" | D5 || Y0_DQ0_5 || data-sort-value="Y0_XDR0_DQ08" | Y0_XDR0_DQ8 || {{pino}} ||  
|-
|-
| data-sort-value="0D06" | D6 || Y0_DQ1_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="0D06" | D6 || Y0_DQ1_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
|-
|-
| data-sort-value="0D07" | D7 || Y0_DQ1_3 || Y0_XDR1_DQ10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D07" | D7 || Y0_DQ1_3 || Y0_XDR1_DQ10 || {{pino}} ||  
|-
|-
| data-sort-value="0D08" | D8 || Y0_DQ1_1 || data-sort-value="Y0_XDR1_DQ06" | Y0_XDR1_DQ6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D08" | D8 || Y0_DQ1_1 || data-sort-value="Y0_XDR1_DQ06" | Y0_XDR1_DQ6 || {{pino}} ||  
|-
|-
| data-sort-value="0D09" | D9 || Y0_DQ0_3 || data-sort-value="Y0_XDR1_DQ02" | Y0_XDR1_DQ2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0D09" | D9 || Y0_DQ0_3 || data-sort-value="Y0_XDR1_DQ02" | Y0_XDR1_DQ2 || {{pino}} ||  
|-
|-
| data-sort-value="0D10" | D10 || Y0_DQ0_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="0D10" | D10 || Y0_DQ0_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
Line 446: Line 446:
| data-sort-value="0F06" | F6 || Y0_RQ_SRD || BE_Y0_RQ_SRD || {{pini}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad C16. Serial data in/out ?
| data-sort-value="0F06" | F6 || Y0_RQ_SRD || BE_Y0_RQ_SRD || {{pini}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad C16. Serial data in/out ?
|-
|-
| data-sort-value="0F07" | F7 || Y0_DQ1N_7 || data-sort-value="Y0_XDR1_DQN00" | Y0_XDR1_DQN0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0F07" | F7 || Y0_DQ1N_7 || data-sort-value="Y0_XDR1_DQN00" | Y0_XDR1_DQN0 || {{pino}} ||  
|-
|-
| data-sort-value="0F08" | F8 || Y0_DQ1N_0 || Y0_XDR1_DQN12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0F08" | F8 || Y0_DQ1N_0 || Y0_XDR1_DQN12 || {{pino}} ||  
|-
|-
| data-sort-value="0F09" | F9 || Y0_DQ0N_7 || data-sort-value="Y0_XDR1_DQN04" | Y0_XDR1_DQN4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0F09" | F9 || Y0_DQ0N_7 || data-sort-value="Y0_XDR1_DQN04" | Y0_XDR1_DQN4 || {{pino}} ||  
|-
|-
| data-sort-value="0F10" | F10 || Y0_DQ0N_2 || data-sort-value="Y0_XDR1_DQN08" | Y0_XDR1_DQN8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0F10" | F10 || Y0_DQ0N_2 || data-sort-value="Y0_XDR1_DQN08" | Y0_XDR1_DQN8 || {{pino}} ||  
|-
|-
| data-sort-value="0F11" | F11 || {{cellcolors|#333|#fff}} YC_SCAN_CLK4 || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0F11" | F11 || {{cellcolors|#333|#fff}} YC_SCAN_CLK4 || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 530: Line 530:
| data-sort-value="0G06" | G6 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0G06" | G6 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0G07" | G7 || Y0_DQ1_7 || data-sort-value="Y0_XDR1_DQ00" | Y0_XDR1_DQ0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0G07" | G7 || Y0_DQ1_7 || data-sort-value="Y0_XDR1_DQ00" | Y0_XDR1_DQ0 || {{pino}} ||  
|-
|-
| data-sort-value="0G08" | G8 || Y0_DQ1_0 || Y0_XDR1_DQ12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0G08" | G8 || Y0_DQ1_0 || Y0_XDR1_DQ12 || {{pino}} ||  
|-
|-
| data-sort-value="0G09" | G9 || Y0_DQ0_7 || data-sort-value="Y0_XDR1_DQ04" | Y0_XDR1_DQ4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0G09" | G9 || Y0_DQ0_7 || data-sort-value="Y0_XDR1_DQ04" | Y0_XDR1_DQ4 || {{pino}} ||  
|-
|-
| data-sort-value="0G10" | G10 || Y0_DQ0_2 || data-sort-value="Y0_XDR1_DQ08" | Y0_XDR1_DQ8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0G10" | G10 || Y0_DQ0_2 || data-sort-value="Y0_XDR1_DQ08" | Y0_XDR1_DQ8 || {{pino}} ||  
|-
|-
| data-sort-value="0G11" | G11 || {{cellcolors|#333|#fff}} YC_SCAN_CLK3 || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0G11" | G11 || {{cellcolors|#333|#fff}} YC_SCAN_CLK3 || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,026: Line 1,026:
| data-sort-value="0N02" | N2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0N02" | N2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0N03" | N3 || Y0_DQ2_4 || Y0_XDR0_DQ11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0N03" | N3 || Y0_DQ2_4 || Y0_XDR0_DQ11 || {{pino}} ||  
|-
|-
| data-sort-value="0N04" | N4 || Y0_DQ2N_4 || Y0_XDR0_DQN11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0N04" | N4 || Y0_DQ2N_4 || Y0_XDR0_DQN11 || {{pino}} ||  
|-
|-
| data-sort-value="0N05" | N5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0N05" | N5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0N06" | N6 || Y0_DQ2_1 || data-sort-value="Y0_XDR0_DQ01" | Y0_XDR0_DQ1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0N06" | N6 || Y0_DQ2_1 || data-sort-value="Y0_XDR0_DQ01" | Y0_XDR0_DQ1 || {{pino}} ||  
|-
|-
| data-sort-value="0N07" | N7 || Y0_DQ2N_1 || data-sort-value="Y0_XDR0_DQN01" | Y0_XDR0_DQN1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0N07" | N7 || Y0_DQ2N_1 || data-sort-value="Y0_XDR0_DQN01" | Y0_XDR0_DQN1 || {{pino}} ||  
|-
|-
| data-sort-value="0N08" | N8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0N08" | N8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,106: Line 1,106:
| data-sort-value="0N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
| data-sort-value="0N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="0P01" | P1 || Y0_DQ2_3 || data-sort-value="Y0_XDR0_DQ07" | Y0_XDR0_DQ7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P01" | P1 || Y0_DQ2_3 || data-sort-value="Y0_XDR0_DQ07" | Y0_XDR0_DQ7 || {{pino}} ||  
|-
|-
| data-sort-value="0P02" | P2 || Y0_DQ2N_3 || data-sort-value="Y0_XDR0_DQN07" | Y0_XDR0_DQN7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P02" | P2 || Y0_DQ2N_3 || data-sort-value="Y0_XDR0_DQN07" | Y0_XDR0_DQN7 || {{pino}} ||  
|-
|-
| data-sort-value="0P03" | P3 || Y0_DQ2_6 || Y0_XDR0_DQ15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P03" | P3 || Y0_DQ2_6 || Y0_XDR0_DQ15 || {{pino}} ||  
|-
|-
| data-sort-value="0P04" | P4 || Y0_DQ2N_6 || Y0_XDR0_DQN15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P04" | P4 || Y0_DQ2N_6 || Y0_XDR0_DQN15 || {{pino}} ||  
|-
|-
| data-sort-value="0P05" | P5 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0P05" | P5 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0P06" | P6 || Y0_DQ2_5 || Y0_XDR0_DQ13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P06" | P6 || Y0_DQ2_5 || Y0_XDR0_DQ13 || {{pino}} ||  
|-
|-
| data-sort-value="0P07" | P7 || Y0_DQ2N_5 || Y0_XDR0_DQN13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0P07" | P7 || Y0_DQ2N_5 || Y0_XDR0_DQN13 || {{pino}} ||  
|-
|-
| data-sort-value="0P08" | P8 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0P08" | P8 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 1,194: Line 1,194:
| data-sort-value="0R02" | R2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0R02" | R2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0R03" | R3 || Y0_DQ3_4 || data-sort-value="Y0_XDR0_DQ03" | Y0_XDR0_DQ3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0R03" | R3 || Y0_DQ3_4 || data-sort-value="Y0_XDR0_DQ03" | Y0_XDR0_DQ3 || {{pino}} ||  
|-
|-
| data-sort-value="0R04" | R4 || Y0_DQ3N_4 || data-sort-value="Y0_XDR0_DQN03" | Y0_XDR0_DQN3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0R04" | R4 || Y0_DQ3N_4 || data-sort-value="Y0_XDR0_DQN03" | Y0_XDR0_DQN3 || {{pino}} ||  
|-
|-
| data-sort-value="0R05" | R5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0R05" | R5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0R06" | R6 || Y0_DQ2_0 || data-sort-value="Y0_XDR0_DQ05" | Y0_XDR0_DQ5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0R06" | R6 || Y0_DQ2_0 || data-sort-value="Y0_XDR0_DQ05" | Y0_XDR0_DQ5 || {{pino}} ||  
|-
|-
| data-sort-value="0R07" | R7 || Y0_DQ2N_0 || data-sort-value="Y0_XDR0_DQN05" | Y0_XDR0_DQN5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0R07" | R7 || Y0_DQ2N_0 || data-sort-value="Y0_XDR0_DQN05" | Y0_XDR0_DQN5 || {{pino}} ||  
|-
|-
| data-sort-value="0R08" | R8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0R08" | R8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,284: Line 1,284:
| data-sort-value="0T05" | T5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0T05" | T5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0T06" | T6 || Y0_DQ3_2 || data-sort-value="Y0_XDR0_DQ09" | Y0_XDR0_DQ9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0T06" | T6 || Y0_DQ3_2 || data-sort-value="Y0_XDR0_DQ09" | Y0_XDR0_DQ9 || {{pino}} ||  
|-
|-
| data-sort-value="0T07" | T7 || Y0_DQ3N_2 || data-sort-value="Y0_XDR0_DQN09" | Y0_XDR0_DQN9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR0 (first chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0T07" | T7 || Y0_DQ3N_2 || data-sort-value="Y0_XDR0_DQN09" | Y0_XDR0_DQN9 || {{pino}} ||  
|-
|-
| data-sort-value="0T08" | T8 || {{cellcolors|#333|#fff}} Y0_DQ2_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0T08" | T8 || {{cellcolors|#333|#fff}} Y0_DQ2_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,362: Line 1,362:
| data-sort-value="0U02" | U2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0U02" | U2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0U03" | U3 || Y0_DQ2_7 || Y0_XDR1_DQ11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0U03" | U3 || Y0_DQ2_7 || Y0_XDR1_DQ11 || {{pino}} ||  
|-
|-
| data-sort-value="0U04" | U4 || Y0_DQ2N_7 || Y0_XDR1_DQN11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0U04" | U4 || Y0_DQ2N_7 || Y0_XDR1_DQN11 || {{pino}} ||  
|-
|-
| data-sort-value="0U05" | U5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0U05" | U5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0U06" | U6 || Y0_DQ2_2 || data-sort-value="Y0_XDR1_DQ01" | Y0_XDR1_DQ1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0U06" | U6 || Y0_DQ2_2 || data-sort-value="Y0_XDR1_DQ01" | Y0_XDR1_DQ1 || {{pino}} ||  
|-
|-
| data-sort-value="0U07" | U7 || Y0_DQ2N_2 || data-sort-value="Y0_XDR1_DQN01" | Y0_XDR1_DQN1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0U07" | U7 || Y0_DQ2N_2 || data-sort-value="Y0_XDR1_DQN01" | Y0_XDR1_DQN1 || {{pino}} ||  
|-
|-
| data-sort-value="0U08" | U8 || {{cellcolors|#c33|#fff}} Y0_DQ2_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
| data-sort-value="0U08" | U8 || {{cellcolors|#c33|#fff}} Y0_DQ2_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
Line 1,442: Line 1,442:
| data-sort-value="0U99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
| data-sort-value="0U99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="0V01" | V1 || Y0_DQ3_0 || data-sort-value="Y0_XDR1_DQ07" | Y0_XDR1_DQ7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V01" | V1 || Y0_DQ3_0 || data-sort-value="Y0_XDR1_DQ07" | Y0_XDR1_DQ7 || {{pino}} ||  
|-
|-
| data-sort-value="0V02" | V2 || Y0_DQ3N_0 || data-sort-value="Y0_XDR1_DQN07" | Y0_XDR1_DQN7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V02" | V2 || Y0_DQ3N_0 || data-sort-value="Y0_XDR1_DQN07" | Y0_XDR1_DQN7 || {{pino}} ||  
|-
|-
| data-sort-value="0V03" | V3 || Y0_DQ3_5 || Y0_XDR1_DQ15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V03" | V3 || Y0_DQ3_5 || Y0_XDR1_DQ15 || {{pino}} ||  
|-
|-
| data-sort-value="0V04" | V4 || Y0_DQ3N_5 || Y0_XDR1_DQN15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V04" | V4 || Y0_DQ3N_5 || Y0_XDR1_DQN15 || {{pino}} ||  
|-
|-
| data-sort-value="0V05" | V5 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0V05" | V5 || {{cellcolors|#d53|#fff}} YC_VDDID || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0V06" | V6 || Y0_DQ3_1 || Y0_XDR1_DQ13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V06" | V6 || Y0_DQ3_1 || Y0_XDR1_DQ13 || {{pino}} ||  
|-
|-
| data-sort-value="0V07" | V7 || Y0_DQ3N_1 || Y0_XDR1_DQN13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0V07" | V7 || Y0_DQ3N_1 || Y0_XDR1_DQN13 || {{pino}} ||  
|-
|-
| data-sort-value="0V08" | V8 || {{cellcolors|#c33|#fff}} Y0_DQ3_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
| data-sort-value="0V08" | V8 || {{cellcolors|#c33|#fff}} Y0_DQ3_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
Line 1,530: Line 1,530:
| data-sort-value="0W02" | W2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="0W02" | W2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="0W03" | W3 || Y0_DQ3_6 || data-sort-value="Y0_XDR1_DQ03" | Y0_XDR1_DQ3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0W03" | W3 || Y0_DQ3_6 || data-sort-value="Y0_XDR1_DQ03" | Y0_XDR1_DQ3 || {{pino}} ||  
|-
|-
| data-sort-value="0W04" | W4 || Y0_DQ3N_6 || data-sort-value="Y0_XDR1_DQN03" | Y0_XDR1_DQN3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0W04" | W4 || Y0_DQ3N_6 || data-sort-value="Y0_XDR1_DQN03" | Y0_XDR1_DQN3 || {{pino}} ||  
|-
|-
| data-sort-value="0W05" | W5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="0W05" | W5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="0W06" | W6 || Y0_DQ3_3 || data-sort-value="Y0_XDR1_DQ05" | Y0_XDR1_DQ5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0W06" | W6 || Y0_DQ3_3 || data-sort-value="Y0_XDR1_DQ05" | Y0_XDR1_DQ5 || {{pino}} ||  
|-
|-
| data-sort-value="0W07" | W7 || Y0_DQ3N_3 || data-sort-value="Y0_XDR1_DQN05" | Y0_XDR1_DQN5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0W07" | W7 || Y0_DQ3N_3 || data-sort-value="Y0_XDR1_DQN05" | Y0_XDR1_DQN5 || {{pino}} ||  
|-
|-
| data-sort-value="0W08" | W8 || {{cellcolors|#333|#fff}} Y0_DQ3_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0W08" | W8 || {{cellcolors|#333|#fff}} Y0_DQ3_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,620: Line 1,620:
| data-sort-value="0Y05" | Y5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0Y05" | Y5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="0Y06" | Y6 || Y0_DQ3_7 || data-sort-value="Y0_XDR1_DQ09" | Y0_XDR1_DQ9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0Y06" | Y6 || Y0_DQ3_7 || data-sort-value="Y0_XDR1_DQ09" | Y0_XDR1_DQ9 || {{pino}} ||  
|-
|-
| data-sort-value="0Y07" | Y7 || Y0_DQ3N_7 || data-sort-value="Y0_XDR1_DQN09" | Y0_XDR1_DQN9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0_XDR1 (second chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="0Y07" | Y7 || Y0_DQ3N_7 || data-sort-value="Y0_XDR1_DQN09" | Y0_XDR1_DQN9 || {{pino}} ||  
|-
|-
| data-sort-value="0Y08" | Y8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="0Y08" | Y8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,788: Line 1,788:
| data-sort-value="AB05" | AB5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AB05" | AB5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AB06" | AB6 || Y1_DQ0_1 || data-sort-value="Y1_XDR1_DQ08" | Y1_XDR1_DQ8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AB06" | AB6 || Y1_DQ0_1 || data-sort-value="Y1_XDR1_DQ08" | Y1_XDR1_DQ8 || {{pino}} ||  
|-
|-
| data-sort-value="AB07" | AB7 || Y1_DQ0N_1 || data-sort-value="Y1_XDR1_DQN08" | Y1_XDR1_DQN8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AB07" | AB7 || Y1_DQ0N_1 || data-sort-value="Y1_XDR1_DQN08" | Y1_XDR1_DQN8 || {{pino}} ||  
|-
|-
| data-sort-value="AB08" | AB8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AB08" | AB8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,866: Line 1,866:
| data-sort-value="AC02" | AC2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AC02" | AC2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="AC03" | AC3 || Y1_DQ0_4 || data-sort-value="Y1_XDR1_DQ02" | Y1_XDR1_DQ2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AC03" | AC3 || Y1_DQ0_4 || data-sort-value="Y1_XDR1_DQ02" | Y1_XDR1_DQ2 || {{pino}} ||  
|-
|-
| data-sort-value="AC04" | AC4 || Y1_DQ0N_4 || data-sort-value="Y1_XDR1_DQN02" | Y1_XDR1_DQN2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AC04" | AC4 || Y1_DQ0N_4 || data-sort-value="Y1_XDR1_DQN02" | Y1_XDR1_DQN2 || {{pino}} ||  
|-
|-
| data-sort-value="AC05" | AC5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AC05" | AC5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="AC06" | AC6 || Y1_DQ0_7 || data-sort-value="Y1_XDR1_DQ04" | Y1_XDR1_DQ4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AC06" | AC6 || Y1_DQ0_7 || data-sort-value="Y1_XDR1_DQ04" | Y1_XDR1_DQ4 || {{pino}} ||  
|-
|-
| data-sort-value="AC07" | AC7 || Y1_DQ0N_7 || data-sort-value="Y1_XDR1_DQN04" | Y1_XDR1_DQN4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AC07" | AC7 || Y1_DQ0N_7 || data-sort-value="Y1_XDR1_DQN04" | Y1_XDR1_DQN4 || {{pino}} ||  
|-
|-
| data-sort-value="AC08" | AC8 || {{cellcolors|#333|#fff}} Y1_DQ0_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AC08" | AC8 || {{cellcolors|#333|#fff}} Y1_DQ0_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 1,946: Line 1,946:
| data-sort-value="AC99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
| data-sort-value="AC99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="AD01" | AD1 || Y1_DQ0_2 || data-sort-value="Y1_XDR1_DQ06" | Y1_XDR1_DQ6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD01" | AD1 || Y1_DQ0_2 || data-sort-value="Y1_XDR1_DQ06" | Y1_XDR1_DQ6 || {{pino}} ||  
|-
|-
| data-sort-value="AD02" | AD2 || Y1_DQ0N_2 || data-sort-value="Y1_XDR1_DQN06" | Y1_XDR1_DQN6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD02" | AD2 || Y1_DQ0N_2 || data-sort-value="Y1_XDR1_DQN06" | Y1_XDR1_DQN6 || {{pino}} ||  
|-
|-
| data-sort-value="AD03" | AD3 || Y1_DQ0_5 || Y1_XDR1_DQ14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD03" | AD3 || Y1_DQ0_5 || Y1_XDR1_DQ14 || {{pino}} ||  
|-
|-
| data-sort-value="AD04" | AD4 || Y1_DQ0N_5 || Y1_XDR1_DQN14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD04" | AD4 || Y1_DQ0N_5 || Y1_XDR1_DQN14 || {{pino}} ||  
|-
|-
| data-sort-value="AD05" | AD5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AD05" | AD5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="AD06" | AD6 || Y1_DQ1_0 || Y1_XDR1_DQ12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD06" | AD6 || Y1_DQ1_0 || Y1_XDR1_DQ12 || {{pino}} ||  
|-
|-
| data-sort-value="AD07" | AD7 || Y1_DQ1N_0 || Y1_XDR1_DQN12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AD07" | AD7 || Y1_DQ1N_0 || Y1_XDR1_DQN12 || {{pino}} ||  
|-
|-
| data-sort-value="AD08" | AD8 || {{cellcolors|#c33|#fff}} Y1_DQ0_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
| data-sort-value="AD08" | AD8 || {{cellcolors|#c33|#fff}} Y1_DQ0_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
Line 2,034: Line 2,034:
| data-sort-value="AE02" | AE2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AE02" | AE2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="AE03" | AE3 || Y1_DQ1_1 || Y1_XDR1_DQ10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AE03" | AE3 || Y1_DQ1_1 || Y1_XDR1_DQ10 || {{pino}} ||  
|-
|-
| data-sort-value="AE04" | AE4 || Y1_DQ1N_1 || Y1_XDR1_DQN10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AE04" | AE4 || Y1_DQ1N_1 || Y1_XDR1_DQN10 || {{pino}} ||  
|-
|-
| data-sort-value="AE05" | AE5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AE05" | AE5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AE06" | AE6 || Y1_DQ1_3 || data-sort-value="Y1_XDR1_DQ00" | Y1_XDR1_DQ0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AE06" | AE6 || Y1_DQ1_3 || data-sort-value="Y1_XDR1_DQ00" | Y1_XDR1_DQ0 || {{pino}} ||  
|-
|-
| data-sort-value="AE07" | AE7 || Y1_DQ1N_3 || data-sort-value="Y1_XDR1_DQN00" | Y1_XDR1_DQN0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AE07" | AE7 || Y1_DQ1N_3 || data-sort-value="Y1_XDR1_DQN00" | Y1_XDR1_DQN0 || {{pino}} ||  
|-
|-
| data-sort-value="AE08" | AE8 || {{cellcolors|#c33|#fff}} Y1_DQ1_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
| data-sort-value="AE08" | AE8 || {{cellcolors|#c33|#fff}} Y1_DQ1_VDDA || +1.5V_BE_YC_VDDA || {{pin}} || data-sort-value="Z1.5V" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SI4866DY-T1-E3/2622290 Vishay Siliconix SI4866DY-T1-E3] pins 1,2,3 through XIO filters
Line 2,124: Line 2,124:
| data-sort-value="AF05" | AF5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AF05" | AF5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AF06" | AF6 || Y1_DQ0_0 || data-sort-value="Y1_XDR0_DQ08" | Y1_XDR0_DQ8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AF06" | AF6 || Y1_DQ0_0 || data-sort-value="Y1_XDR0_DQ08" | Y1_XDR0_DQ8 || {{pino}} ||  
|-
|-
| data-sort-value="AF07" | AF7 || Y1_DQ0N_0 || data-sort-value="Y1_XDR0_DQN08" | Y1_XDR0_DQN8 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AF07" | AF7 || Y1_DQ0N_0 || data-sort-value="Y1_XDR0_DQN08" | Y1_XDR0_DQN8 || {{pino}} ||  
|-
|-
| data-sort-value="AF08" | AF8 || {{cellcolors|#333|#fff}} Y1_DQ1_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AF08" | AF8 || {{cellcolors|#333|#fff}} Y1_DQ1_GNDA || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 2,202: Line 2,202:
| data-sort-value="AG02" | AG2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AG02" | AG2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="AG03" | AG3 || Y1_DQ0_6 || data-sort-value="Y1_XDR0_DQ02" | Y1_XDR0_DQ2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AG03" | AG3 || Y1_DQ0_6 || data-sort-value="Y1_XDR0_DQ02" | Y1_XDR0_DQ2 || {{pino}} ||  
|-
|-
| data-sort-value="AG04" | AG4 || Y1_DQ0N_6 || data-sort-value="Y1_XDR0_DQN02" | Y1_XDR0_DQN2 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AG04" | AG4 || Y1_DQ0N_6 || data-sort-value="Y1_XDR0_DQN02" | Y1_XDR0_DQN2 || {{pino}} ||  
|-
|-
| data-sort-value="AG05" | AG5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AG05" | AG5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="AG06" | AG6 || Y1_DQ1_2 || data-sort-value="Y1_XDR0_DQ04" | Y1_XDR0_DQ4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AG06" | AG6 || Y1_DQ1_2 || data-sort-value="Y1_XDR0_DQ04" | Y1_XDR0_DQ4 || {{pino}} ||  
|-
|-
| data-sort-value="AG07" | AG7 || Y1_DQ1N_2 || data-sort-value="Y1_XDR0_DQN04" | Y1_XDR0_DQN4 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AG07" | AG7 || Y1_DQ1N_2 || data-sort-value="Y1_XDR0_DQN04" | Y1_XDR0_DQN4 || {{pino}} ||  
|-
|-
| data-sort-value="AG08" | AG8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AG08" | AG8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 2,282: Line 2,282:
| data-sort-value="AG99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
| data-sort-value="AG99" style="padding:0px" | || colspan="4" data-sort-value="ZZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="AH01" | AH1 || Y1_DQ0_3 || data-sort-value="Y1_XDR0_DQ06" | Y1_XDR0_DQ6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH01" | AH1 || Y1_DQ0_3 || data-sort-value="Y1_XDR0_DQ06" | Y1_XDR0_DQ6 || {{pino}} ||  
|-
|-
| data-sort-value="AH02" | AH2 || Y1_DQ0N_3 || data-sort-value="Y1_XDR0_DQN06" | Y1_XDR0_DQN6 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH02" | AH2 || Y1_DQ0N_3 || data-sort-value="Y1_XDR0_DQN06" | Y1_XDR0_DQN6 || {{pino}} ||  
|-
|-
| data-sort-value="AH03" | AH3 || Y1_DQ1_5 || Y1_XDR0_DQ14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH03" | AH3 || Y1_DQ1_5 || Y1_XDR0_DQ14 || {{pino}} ||  
|-
|-
| data-sort-value="AH04" | AH4 || Y1_DQ1N_5 || Y1_XDR0_DQN14 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH04" | AH4 || Y1_DQ1N_5 || Y1_XDR0_DQN14 || {{pino}} ||  
|-
|-
| data-sort-value="AH05" | AH5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AH05" | AH5 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="AH06" | AH6 || Y1_DQ1_4 || Y1_XDR0_DQ12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH06" | AH6 || Y1_DQ1_4 || Y1_XDR0_DQ12 || {{pino}} ||  
|-
|-
| data-sort-value="AH07" | AH7 || Y1_DQ1N_4 || Y1_XDR0_DQN12 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AH07" | AH7 || Y1_DQ1N_4 || Y1_XDR0_DQN12 || {{pino}} ||  
|-
|-
| data-sort-value="AH08" | AH8 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AH08" | AH8 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 2,370: Line 2,370:
| data-sort-value="AJ02" | AJ2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AJ02" | AJ2 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="AJ03" | AJ3 || Y1_DQ1_7 || Y1_XDR0_DQ10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AJ03" | AJ3 || Y1_DQ1_7 || Y1_XDR0_DQ10 || {{pino}} ||  
|-
|-
| data-sort-value="AJ04" | AJ4 || Y1_DQ1N_7 || Y1_XDR0_DQN10 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AJ04" | AJ4 || Y1_DQ1N_7 || Y1_XDR0_DQN10 || {{pino}} ||  
|-
|-
| data-sort-value="AJ05" | AJ5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AJ05" | AJ5 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AJ06" | AJ6 || Y1_DQ1_6 || data-sort-value="Y1_XDR0_DQ00" | Y1_XDR0_DQ0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AJ06" | AJ6 || Y1_DQ1_6 || data-sort-value="Y1_XDR0_DQ00" | Y1_XDR0_DQ0 || {{pino}} ||  
|-
|-
| data-sort-value="AJ07" | AJ7 || Y1_DQ1N_6 || data-sort-value="Y1_XDR0_DQN00" | Y1_XDR0_DQN0 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AJ07" | AJ7 || Y1_DQ1N_6 || data-sort-value="Y1_XDR0_DQN00" | Y1_XDR0_DQN0 || {{pino}} ||  
|-
|-
| data-sort-value="AJ08" | AJ8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AJ08" | AJ8 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 2,882: Line 2,882:
| data-sort-value="AR06" | AR6 || Y1_RQ_SCK || BE_Y1_RQ_SCK || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip), and Y1_XDR1 (fourth chip) pad J15. Serial clock
| data-sort-value="AR06" | AR6 || Y1_RQ_SCK || BE_Y1_RQ_SCK || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip), and Y1_XDR1 (fourth chip) pad J15. Serial clock
|-
|-
| data-sort-value="AR07" | AR7 || Y1_DQ2_2 || data-sort-value="Y1_XDR1_DQ01" | Y1_XDR1_DQ1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AR07" | AR7 || Y1_DQ2_2 || data-sort-value="Y1_XDR1_DQ01" | Y1_XDR1_DQ1 || {{pino}} ||  
|-
|-
| data-sort-value="AR08" | AR8 || Y1_DQ2_7 || Y1_XDR1_DQ13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AR08" | AR8 || Y1_DQ2_7 || Y1_XDR1_DQ13 || {{pino}} ||  
|-
|-
| data-sort-value="AR09" | AR9 || Y1_DQ3_0 || data-sort-value="Y1_XDR1_DQ05" | Y1_XDR1_DQ5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AR09" | AR9 || Y1_DQ3_0 || data-sort-value="Y1_XDR1_DQ05" | Y1_XDR1_DQ5 || {{pino}} ||  
|-
|-
| data-sort-value="AR10" | AR10 || Y1_DQ3_7 || data-sort-value="Y1_XDR1_DQ09" | Y1_XDR1_DQ9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AR10" | AR10 || Y1_DQ3_7 || data-sort-value="Y1_XDR1_DQ09" | Y1_XDR1_DQ9 || {{pino}} ||  
|-
|-
| data-sort-value="AR11" | AR11 || {{cellcolors|#333|#fff}} YC_XCLK_EN || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AR11" | AR11 || {{cellcolors|#333|#fff}} YC_XCLK_EN || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 2,966: Line 2,966:
| data-sort-value="AT06" | AT6 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AT06" | AT6 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AT07" | AT7 || Y1_DQ2N_2 || data-sort-value="Y1_XDR1_DQN01" | Y1_XDR1_DQN1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AT07" | AT7 || Y1_DQ2N_2 || data-sort-value="Y1_XDR1_DQN01" | Y1_XDR1_DQN1 || {{pino}} ||  
|-
|-
| data-sort-value="AT08" | AT8 || Y1_DQ2N_7 || Y1_XDR1_DQN13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AT08" | AT8 || Y1_DQ2N_7 || Y1_XDR1_DQN13 || {{pino}} ||  
|-
|-
| data-sort-value="AT09" | AT9 || Y1_DQ3N_0 || data-sort-value="Y1_XDR1_DQN05" | Y1_XDR1_DQN5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AT09" | AT9 || Y1_DQ3N_0 || data-sort-value="Y1_XDR1_DQN05" | Y1_XDR1_DQN5 || {{pino}} ||  
|-
|-
| data-sort-value="AT10" | AT10 || Y1_DQ3N_7 || data-sort-value="Y1_XDR1_DQN09" | Y1_XDR1_DQN9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AT10" | AT10 || Y1_DQ3N_7 || data-sort-value="Y1_XDR1_DQN09" | Y1_XDR1_DQN9 || {{pino}} ||  
|-
|-
| data-sort-value="AT11" | AT11 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AT11" | AT11 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
Line 3,124: Line 3,124:
| data-sort-value="AV01" | AV1 || Y1_DQ2_RLOAD || BE_Y1_DQ2_RLOAD || {{pini}} || Resistor 49.9 ohms to +1.2V_YC_RC_VDDIO
| data-sort-value="AV01" | AV1 || Y1_DQ2_RLOAD || BE_Y1_DQ2_RLOAD || {{pini}} || Resistor 49.9 ohms to +1.2V_YC_RC_VDDIO
|-
|-
| data-sort-value="AV02" | AV2 || Y1_DQ2_1 || data-sort-value="Y1_XDR0_DQ01" | Y1_XDR0_DQ1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV02" | AV2 || Y1_DQ2_1 || data-sort-value="Y1_XDR0_DQ01" | Y1_XDR0_DQ1 || {{pino}} ||  
|-
|-
| data-sort-value="AV03" | AV3 || Y1_DQ2_5 || Y1_XDR0_DQ13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV03" | AV3 || Y1_DQ2_5 || Y1_XDR0_DQ13 || {{pino}} ||  
|-
|-
| data-sort-value="AV04" | AV4 || Y1_DQ2_0 || data-sort-value="Y1_XDR0_DQ05" | Y1_XDR0_DQ5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV04" | AV4 || Y1_DQ2_0 || data-sort-value="Y1_XDR0_DQ05" | Y1_XDR0_DQ5 || {{pino}} ||  
|-
|-
| data-sort-value="AV05" | AV5 || Y1_DQ3_4 || data-sort-value="Y1_XDR0_DQ09" | Y1_XDR0_DQ9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV05" | AV5 || Y1_DQ3_4 || data-sort-value="Y1_XDR0_DQ09" | Y1_XDR0_DQ9 || {{pino}} ||  
|-
|-
| data-sort-value="AV06" | AV6 || Y1_DQ2_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="AV06" | AV6 || Y1_DQ2_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
|-
|-
| data-sort-value="AV07" | AV7 || Y1_DQ2_3 || Y1_XDR1_DQ11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV07" | AV7 || Y1_DQ2_3 || Y1_XDR1_DQ11 || {{pino}} ||  
|-
|-
| data-sort-value="AV08" | AV8 || Y1_DQ3_1 || data-sort-value="Y1_XDR1_DQ07" | Y1_XDR1_DQ7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV08" | AV8 || Y1_DQ3_1 || data-sort-value="Y1_XDR1_DQ07" | Y1_XDR1_DQ7 || {{pino}} ||  
|-
|-
| data-sort-value="AV09" | AV9 || Y1_DQ3_3 || data-sort-value="Y1_XDR1_DQ03" | Y1_XDR1_DQ3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AV09" | AV9 || Y1_DQ3_3 || data-sort-value="Y1_XDR1_DQ03" | Y1_XDR1_DQ3 || {{pino}} ||  
|-
|-
| data-sort-value="AV10" | AV10 || Y1_DQ3_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="AV10" | AV10 || Y1_DQ3_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
Line 3,208: Line 3,208:
| data-sort-value="AW01" | AW1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
| data-sort-value="AW01" | AW1 || {{cellcolors|#333|#fff}} GND || GND || {{pin}} || data-sort-value="ZGND" {{cellcolors||#888}} Ground
|-
|-
| data-sort-value="AW02" | AW2 || Y1_DQ2N_1 || data-sort-value="Y1_XDR0_DQN01" | Y1_XDR0_DQN1 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW02" | AW2 || Y1_DQ2N_1 || data-sort-value="Y1_XDR0_DQN01" | Y1_XDR0_DQN1 || {{pino}} ||  
|-
|-
| data-sort-value="AW03" | AW3 || Y1_DQ2N_5 || Y1_XDR0_DQN13 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW03" | AW3 || Y1_DQ2N_5 || Y1_XDR0_DQN13 || {{pino}} ||  
|-
|-
| data-sort-value="AW04" | AW4 || Y1_DQ2N_0 || data-sort-value="Y1_XDR0_DQN05" | Y1_XDR0_DQN5 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW04" | AW4 || Y1_DQ2N_0 || data-sort-value="Y1_XDR0_DQN05" | Y1_XDR0_DQN5 || {{pino}} ||  
|-
|-
| data-sort-value="AW05" | AW5 || Y1_DQ3N_4 || data-sort-value="Y1_XDR0_DQN09" | Y1_XDR0_DQN9 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW05" | AW5 || Y1_DQ3N_4 || data-sort-value="Y1_XDR0_DQN09" | Y1_XDR0_DQN9 || {{pino}} ||  
|-
|-
| data-sort-value="AW06" | AW6 || Y1_DQ2N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="AW06" | AW6 || Y1_DQ2N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
|-
|-
| data-sort-value="AW07" | AW7 || Y1_DQ2N_3 || Y1_XDR1_DQN11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW07" | AW7 || Y1_DQ2N_3 || Y1_XDR1_DQN11 || {{pino}} ||  
|-
|-
| data-sort-value="AW08" | AW8 || Y1_DQ3N_1 || data-sort-value="Y1_XDR1_DQN07" | Y1_XDR1_DQN7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW08" | AW8 || Y1_DQ3N_1 || data-sort-value="Y1_XDR1_DQN07" | Y1_XDR1_DQN7 || {{pino}} ||  
|-
|-
| data-sort-value="AW09" | AW9 || Y1_DQ3N_3 || data-sort-value="Y1_XDR1_DQN03" | Y1_XDR1_DQN3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AW09" | AW9 || Y1_DQ3N_3 || data-sort-value="Y1_XDR1_DQN03" | Y1_XDR1_DQN3 || {{pino}} ||  
|-
|-
| data-sort-value="AW10" | AW10 || Y1_DQ3N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
| data-sort-value="AW10" | AW10 || Y1_DQ3N_8 || data-sort-value="ZZ" {{cellcolors|#eee|#888}} N/C || data-sort-value="ZZ" {{pinnc}} || data-sort-value="ZZ" {{cellcolors||#888}} Not Connected
Line 3,292: Line 3,292:
| data-sort-value="AY01" | AY1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AY01" | AY1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="AY02" | AY2 || Y1_DQ2_4 || Y1_XDR0_DQ11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AY02" | AY2 || Y1_DQ2_4 || Y1_XDR0_DQ11 || {{pino}} ||  
|-
|-
| data-sort-value="AY03" | AY3 || Y1_DQ2_6 || data-sort-value="Y1_XDR0_DQ07" | Y1_XDR0_DQ7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AY03" | AY3 || Y1_DQ2_6 || data-sort-value="Y1_XDR0_DQ07" | Y1_XDR0_DQ7 || {{pino}} ||  
|-
|-
| data-sort-value="AY04" | AY4 || Y1_DQ3_2 || Y1_XDR0_DQ15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AY04" | AY4 || Y1_DQ3_2 || Y1_XDR0_DQ15 || {{pino}} ||  
|-
|-
| data-sort-value="AY05" | AY5 || Y1_DQ3_5 || data-sort-value="Y1_XDR0_DQ03" | Y1_XDR0_DQ3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AY05" | AY5 || Y1_DQ3_5 || data-sort-value="Y1_XDR0_DQ03" | Y1_XDR0_DQ3 || {{pino}} ||  
|-
|-
| data-sort-value="AY06" | AY6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="AY06" | AY6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 3,304: Line 3,304:
| data-sort-value="AY07" | AY7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AY07" | AY7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="AY08" | AY8 || Y1_DQ3_6 || Y1_XDR1_DQ15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="AY08" | AY8 || Y1_DQ3_6 || Y1_XDR1_DQ15 || {{pino}} ||  
|-
|-
| data-sort-value="AY09" | AY9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="AY09" | AY9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
Line 3,376: Line 3,376:
| data-sort-value="BA01" | BA1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="BA01" | BA1 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
|-
|-
| data-sort-value="BA02" | BA2 || Y1_DQ2N_4 || Y1_XDR0_DQN11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="BA02" | BA2 || Y1_DQ2N_4 || Y1_XDR0_DQN11 || {{pino}} ||  
|-
|-
| data-sort-value="BA03" | BA3 || Y1_DQ2N_6 || data-sort-value="Y1_XDR0_DQN07" | Y1_XDR0_DQN7 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="BA03" | BA3 || Y1_DQ2N_6 || data-sort-value="Y1_XDR0_DQN07" | Y1_XDR0_DQN7 || {{pino}} ||  
|-
|-
| data-sort-value="BA04" | BA4 || Y1_DQ3N_2 || Y1_XDR0_DQN15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="BA04" | BA4 || Y1_DQ3N_2 || Y1_XDR0_DQN15 || {{pino}} ||  
|-
|-
| data-sort-value="BA05" | BA5 || Y1_DQ3N_5 || data-sort-value="Y1_XDR0_DQN03" | Y1_XDR0_DQN3 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR0 (third chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="BA05" | BA5 || Y1_DQ3N_5 || data-sort-value="Y1_XDR0_DQN03" | Y1_XDR0_DQN3 || {{pino}} ||  
|-
|-
| data-sort-value="BA06" | BA6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
| data-sort-value="BA06" | BA6 || {{cellcolors|#d53|#fff}} YC_VDDIO || +1.2V_YC_RC_VDDIO || {{pin}} || data-sort-value="Z1.2V_YC" | Connected to [https://www.digikey.com/en/products/detail/vishay-siliconix/SUD40N02-08-E3/2623039 Vishay Siliconix SUD40N02-08-E3] pin 3
Line 3,388: Line 3,388:
| data-sort-value="BA07" | BA7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="BA07" | BA7 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
|-
|-
| data-sort-value="BA08" | BA8 || Y1_DQ3N_6 || Y1_XDR1_DQN15 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y1_XDR1 (fourth chip) pad <abbr title="Unknown">UNK</abbr>
| data-sort-value="BA08" | BA8 || Y1_DQ3N_6 || Y1_XDR1_DQN15 || {{pino}} ||  
|-
|-
| data-sort-value="BA09" | BA9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
| data-sort-value="BA09" | BA9 || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZZZ" {{cellcolors||#888}} Missing pad
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