Editing Template:Syscon pinout BGA 200 pads

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| data-sort-value="D03" | D3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad
| data-sort-value="D03" | D3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="ZNA" style="color:#888" | Missing pad
|-
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| data-sort-value="D04" | D4 || O || XDR_FET_RST || {{pino}} || Connected to XDRAM chips pin C15 (XDR_RQ_RST)
| data-sort-value="D04" | D4 || O || XDR_FET_RST || ? || XDR_RQ_RST
|-
|-
| data-sort-value="D05" | D5 || O || XCG_EN || ? || Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)<br>Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)<br>Connected to [[Timebases#ICS_ICS9214DGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9214DGLFT]] (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N)
| data-sort-value="D05" | D5 || O || XCG_EN || ? || Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)<br>Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)<br>Connected to [[Timebases#ICS_ICS9214DGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9214DGLFT]] (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N)
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| data-sort-value="M09" | M9 || G || BUZZER || {{pino}} || Connected to Buzzer (BZ4001) through transistor DTC143ZUA-T106 (Q4014)
| data-sort-value="M09" | M9 || G || BUZZER || {{pino}} || Connected to Buzzer (BZ4001) through transistor DTC143ZUA-T106 (Q4014)
|-
|-
| data-sort-value="M10" | M10 || G || XDR_FET_VREF || {{pino}} || Connected to transistor DTC144EUA-T106 (Q4008). Switches XDR_RQ_VREF_FET
| data-sort-value="M10" | M10 || G || XDR_FET_VREF || ? || Connected to transistor DTC144EUA-T106 (Q4008). Switches XDR_RQ_VREF_FET
|-
|-
| data-sort-value="M11" | M11 || G || SW_ATA || ? || Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)<br>Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)<br>Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD)
| data-sort-value="M11" | M11 || G || SW_ATA || ? || Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)<br>Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)<br>Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD)
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| data-sort-value="N09" | N9 || G || SW_PWM || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 2
| data-sort-value="N09" | N9 || G || SW_PWM || ? || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 2
|-
|-
| data-sort-value="N10" | N10 || G || XDR_FET_SCK || {{pino}} || Connected to transistor SST222AT116 (Q1302) BE_RQ_SCK_BJT
| data-sort-value="N10" | N10 || G || XDR_FET_SCK || ? || BE_RQ_SCK_BJT
|-
|-
| data-sort-value="N11" | N11 || G || SW_4_A || {{pino}} || Connected to wifi board connector (CN3701) pin 9 (11G_PWR_EN)<br>Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller)
| data-sort-value="N11" | N11 || G || SW_4_A || {{pino}} || Connected to wifi board connector (CN3701) pin 9 (11G_PWR_EN)<br>Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller)
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