Template:Elpida memory product code: Difference between revisions
Jump to navigation
Jump to search
mNo edit summary |
No edit summary |
||
| Line 3: | Line 3: | ||
! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code<br>(<abbr title="Some products doesnt includes this code">optional</abbr>) !! Enviroment Code | ! Product Family !! Density !! Organization !! Power Supply, Interface !! Die Rev. !! Package !! Speed !! Internal Code<br>(<abbr title="Some products doesnt includes this code">optional</abbr>) !! Enviroment Code | ||
|- | |- | ||
| '''X''': XDR DRAM<br>'''W''': | | '''X''': XDR DRAM<br>'''W''': GDDR5 SDRAM | ||
| '''51''': 512M<br />'''10''': 1Gb<br>'''11''': ? | | '''51''': 512M<br />'''10''': 1Gb<br>'''11''': ? | ||
| '''16''': x16bit<br />'''32''': x32bit | | '''16''': x16bit<br />'''32''': x32bit | ||
Revision as of 14:41, 11 February 2023
| Product Family | Density | Organization | Power Supply, Interface | Die Rev. | Package | Speed | Internal Code (optional) |
Enviroment Code |
|---|---|---|---|---|---|---|---|---|
| X: XDR DRAM W: GDDR5 SDRAM |
51: 512M 10: 1Gb 11: ? |
16: x16bit 32: x32bit |
A: 1.8V, DRSL B: 1.5V +/- 0.075V, DRSL |
A: Rev1 B: Rev2 C: Rev3 D: Rev4 |
SE: FBGA BG: FBGA ? |
3C: 3.2Gbps (tRAC = 35ns, C Bin) 4D: 4.0Gbps (tRAC = 34ns, D Bin) 28: ? |
A2: ? | E: Lead Free F: Lead & Halogen Free |