Editing Timebases
Jump to navigation
Jump to search
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
Latest revision | Your text | ||
Line 1: | Line 1: | ||
== IDT 6V41265NLG == | == IDT 6V41265NLG == | ||
This is a custom order clock synthesizer, possibly generating clock signals for a | This is a custom order clock synthesizer, possibly generating clock signals for a PCI-Express link between [[MediaCon]] and the [[APU]]. | ||
{| class="wikitable" | {| class="wikitable" | ||
Line 19: | Line 19: | ||
| NL || Package | | NL || Package | ||
|- | |- | ||
| G || Lead Free | |G || Lead Free | ||
|- | |||
|} | |} | ||
https://www.idt.com/document/ovr/timing-solutions-overview (Shows Part Number Legends at the end) | |||
== 39A207 == | |||
seen with markings "39A207 1328 E1 3FU" and "39A207 1333 E1 3PZ" | |||
<gallery> | |||
File:CUH-10xxA - SAA-001 - 39A207 - markings 39A207 1333 E1 3PZ.jpg|[[CUH-10xxA]] [[SAA-001]] 39A207 - markings: 39A207 1333 E1 3PZ | |||
</gallery> | |||
{{Motherboard Components}} | {{Motherboard Components}} | ||
<noinclude>[[Category:Main]]</noinclude> | <noinclude>[[Category:Main]]</noinclude> |