Editing CPU

Jump to navigation Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.

Latest revision Your text
Line 1: Line 1:
== Overview ==
== Overview ==
'''LSI CoreWare CW33300-based core'''
* MIPS R3000A-compatible 32-bit RISC CPU MIPS R3051 with 5 KB L1 cache, running at 33.8688 MHz
* The microprocessor was manufactured by LSI Logic Corp. with technology licensed from SGI
* Features:
** Initial feature size (process node) was 0.5 micron (500 nm)
** 850k – 1M transistors
** Operating performance: 30 MIPS
** Bus bandwidth 132 MB/s
** One arithmetic/logic unit (ALU)
** One shifter
* CPU cache:
** 4 KB instruction cache
** 1 KB non-associative SRAM data cache
'''Geometry Transformation Engine (GTE)'''
* Coprocessor that resides inside the main CPU processor, giving it additional vector math instructions used for 3D graphics, lighting, geometry, polygon and coordinate transformations - GTE performs high-speed matrix multiplications
* Operating performance: 66 MIPS
* Polygons per second (rendered in hardware):
** 90,000 with texture mapping, lighting and Gouraud shading
** 180,000 with texture mapping
** 360,000 with flat shading
'''Motion Decoder (MDEC)'''
* Also residing within the main CPU, enables full screen, high quality FMV playback and is responsible for decompressing images and video into VRAM
* Operating performance: 80 MIPS
* Documented device mode is to read three RLE-encoded 16×16 macroblocks, run IDCT and assemble a single 16×16 RGB macroblock
* Output data may be transferred directly to GPU via DMA
* It is possible to overwrite IDCT matrix and some additional parameters, however MDEC internal instruction set was never documented
* It is directly connected to a CPU bus
'''System Control Coprocessor (Cop0)'''
* This unit is part of the CPU. Has 16 32-bit control registers
* Modified from the original R3000A cop0 architecture, with the addition of a few registers and functions
* Controls memory management through virtual memory technique, system interrupts, exception handling, and breakpoints


== Revisions ==
== Revisions ==
Please note that all contributions to PS1 Developer wiki are considered to be released under the GNU Free Documentation License 1.2 (see PS1 Developer wiki:Copyrights for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource. Do not submit copyrighted work without permission!

To protect the wiki against automated edit spam, we kindly ask you to solve the following hCaptcha:

Cancel Editing help (opens in new window)
Retrieved from "http://www.psdevwiki.com/ps1/CPU"