CPU: Difference between revisions

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===Overview===
Clock frequency: 294 MHz, 299 MHz (later versions)
 
Instruction set: MIPS III, MIPS IV subset, 107 vector instructions
 
2-issue, 2 64-bit fixed point units, 1 floating point unit, 6 stage pipeline
 
Instruction cache: 16 KB, 2-way set associative
 
Data cache: 8 KB, 2-way set associative
 
Scratchpad RAM: 16 KB
 
Translation look aside buffer: 48-entry combined instruction/data
 
Vector processing unit: 4 FMAC units, 1 FDIV unit
 
Vector processing unit registers: 128-bit wide, 32 entries
 
Image processing unit: MPEG2 macroblock layer decoder
 
Direct memory access: 10 channels
 
VDD Voltage: 1.8 V
 
Power consumption: 15 W at 1.8 V
 
Embedded memory: 1 KB RAM, 4 KB FeRAM, 16 KB ROM[9]


===Changes===
===Changes===

Latest revision as of 00:28, 18 July 2023

Clock frequency: 294 MHz, 299 MHz (later versions)

Instruction set: MIPS III, MIPS IV subset, 107 vector instructions

2-issue, 2 64-bit fixed point units, 1 floating point unit, 6 stage pipeline

Instruction cache: 16 KB, 2-way set associative

Data cache: 8 KB, 2-way set associative

Scratchpad RAM: 16 KB

Translation look aside buffer: 48-entry combined instruction/data

Vector processing unit: 4 FMAC units, 1 FDIV unit

Vector processing unit registers: 128-bit wide, 32 entries

Image processing unit: MPEG2 macroblock layer decoder

Direct memory access: 10 channels

VDD Voltage: 1.8 V

Power consumption: 15 W at 1.8 V

Embedded memory: 1 KB RAM, 4 KB FeRAM, 16 KB ROM[9]

Changes[edit | edit source]