Editing Boot Order
Jump to navigation
Jump to search
The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.
| Latest revision | Your text | ||
| Line 1: | Line 1: | ||
[[Category:Software]] | |||
== Boot Sequence == | == Boot Sequence == | ||
Power on: syscon boots from | Power on : syscon boots from it's internal (non-encrypted / dual banked) ROM *1 *2 | ||
+ syscon powers up various power subsystems | + syscon powers up various power subsystems | ||
+ syscon powers up cell and checks status | + syscon powers up cell and checks status | ||
+ syscon sends Cell configuration ring to Cell | + syscon sends Cell configuration ring to Cell | ||
+ syscon pulls the reset of Cell high -> Cell INIT | + syscon pulls the reset of Cell high -> Cell INIT | ||
Cell INIT: CELL boots from | Cell INIT: CELL boots from it's internal ROM *2 | ||
+ fetches encrypted bootldr off NAND (at address 0x000000) /NOR flash (at address 0xFC0000) | + Initialises I/O | ||
+ fetches encrypted bootldr off NAND (at address 0x000000) /NOR flash (at address 0xFC0000) | |||
+ | + Initialises RAM | ||
+ | + loads bootldr into Isolated SPU (SPE0) | ||
+ Runtime Secure Boot decrypts and verifies bootldr and executes | |||
+ bootldr decrypts lv0 which runs on PPU -> loaders INIT | + bootldr decrypts lv0 which runs on PPU -> loaders INIT | ||
loaders INIT: lv0 loads metldr (SPE2) | loaders INIT: lv0 loads metldr (SPE2) | ||
+ passes lv1ldr (which loads lv1) to metldr | + passes lv1ldr (which loads lv1) to metldr | ||
| Line 22: | Line 21: | ||
*1) Read/Writeable with undocumented / should also be read/writeable through serial port and possible to switch it to the backup bank1 with backup_mode pulled high | *1) Read/Writeable with undocumented / should also be read/writeable through serial port and possible to switch it to the backup bank1 with backup_mode pulled high | ||
*2) | *2) CEX/Retail consoles go to standby with red light. SEX/SHOP/SECH will not standby, but instead boot through without waiting for powerbutton. Also check is done on all models if update is flagged to set it into firmware updating procedure | ||
*3) Partialy Read/Writeable | *3) Partialy Read/Writeable | ||
about the disabled SPE: syscon reads it’s internal (non-encrypted) eeprom @ 0x48C30 which is value 0×06 on all | about the disabled SPE: syscon reads it’s internal (non-encrypted) eeprom @ 0x48C30 which is value 0×06 on all CEX/Retail consoles and will set the cell config ring accordingly for 7 SPE’s. SPE0 and SPE2 are reserved for bootldr and metldr for isolation respectively. Setting the value to a nonworking state (e.g. 0×00, 0xFF, enabling a defective SPE or disabling a needed SPE for proper boot) might brick the console, locking you out from restoring the correct value to the syscon eeprom. | ||
=== References === | === References === | ||
* [http://ip.com/patapp/US20090055637 Secure power-on reset engine] | * [http://ip.com/patapp/US20090055637 Secure power-on reset engine] | ||
** [ | ** [http://www.ps3devwiki.com/files/documents/US7895426.pdf US7895426.pdf] | ||
** [ | ** [http://www.ps3devwiki.com/files/documents/US20090055637.pdf US20090055637.pdf] | ||
* [ | * [http://www.ps3devwiki.com/files/documents/-%20Cell%20BE/CellBE_Handbook_v1.12_3Apr09_pub.pdf CellBE_Handbook_v1.12_3Apr09_pub.pdf] | ||
* [ | * [http://www.ps3devwiki.com/files/documents/-%20Cell%20BE/Cell_Broadband_Engine_processor_vault_security_architecture.pdf Cell_Broadband_Engine_processor_vault_security_architecture.pdf] | ||
* [http://www.multiupload.com/7STWIQ8PBF CellBEBootprocess.pdf (177.69 KB) | * [http://www.multiupload.com/7STWIQ8PBF CellBEBootprocess.pdf (177.69 KB)]) // | ||
* [ | * [http://www.ps3devwiki.com/files/documents/-%20CELL%20SDK%20Documentation/lib/CBE_Secure_SDK_Guide_v3.0.pdf CBE_Secure_SDK_Guide_v3.0.pdf] | ||
* [ | * [http://www.ps3devwiki.com/files/documents/-%20Cell%20BE/CellBE_HIG_65nm_v1.01_8Jun2007.pdf CellBE_HIG_65nm_v1.01_8Jun2007.pdf)] | ||
* [ | * [http://www.ps3devwiki.com/files/documents/-%20Cell%20BE/CellBE_HIG_90nm_v1.5_30Nov2007_pub.pdf CellBE_HIG_90nm_v1.5_30Nov2007_pub.pdf]) | ||
* [ | * [http://www.ps3devwiki.com/files/documents/BE_Hardwar_Init_Guide_v1.3_31March2006.pdf BE_Hardwar_Init_Guide_v1.3_31March2006.pdf] | ||
== Chain of Trust == | == Chain of Trust == | ||
| Line 63: | Line 62: | ||
| SPE(0) | | SPE(0) | ||
| Per Console Encrypted at factory | | Per Console Encrypted at factory | ||
| No <span style="color:red | | No <span style="color:red;">*</span> | ||
| No | |||
| Setup Primairy Hardware + load lv0 | |||
| No | | No | ||
|- | |- | ||
| lv0 (Level 0) | | lv0 (Level 0) | ||
| Line 75: | Line 74: | ||
| No | | No | ||
| Setup Hardware | | Setup Hardware | ||
| | | No | ||
|- | |- | ||
| metldr (asecure_loader) | | metldr (asecure_loader) | ||
| Line 81: | Line 80: | ||
| SPE(2) | | SPE(2) | ||
| Per Console Encrypted at factory | | Per Console Encrypted at factory | ||
| No <span style="color:red | | No <span style="color:red;">*</span> | ||
| No | | No | ||
| | | load loaders (Meta Loader) | ||
| Yes | | Yes | ||
|- | |- | ||
| Line 92: | Line 91: | ||
| Yes | | Yes | ||
| No | | No | ||
| Decrypt lv1 (Hypervisor) | | Decrypt lv1 (Hypervisor) | ||
| Yes | | Yes | ||
|- | |- | ||
| Line 131: | Line 130: | ||
| Yes | | Yes | ||
|} | |} | ||
<span style="color:red | <span style="color:red;">*</span> : ofcourse with new hardware revisions, it is updated in factory. See [[Flash#new_metldr.2]] | ||
== Chain of trust Diagram == | == Chain of trust Diagram == | ||
| Line 140: | Line 139: | ||
* http://www.ibm.com/developerworks/power/library/pa-cellsecurity/ | * http://www.ibm.com/developerworks/power/library/pa-cellsecurity/ | ||
== Changes in firmware 3.60 == | == Changes in firmware 3.60 == | ||
Lv0 has now been changed, LV0 now appears to encapsulate all of the [[Loaders]] (appldr, isoldr, lv1ldr, lv2ldr). Now in order to break the chain of trust we need to be able to decrypt/exploit LV0 (or bootldr which loads LV0) | Lv0 has now been changed, LV0 now appears to encapsulate all of the [[Loaders]] (appldr, isoldr, lv1ldr, lv2ldr). Now in order to break the chain of trust we need to be able to decrypt/exploit LV0 (or bootldr which loads LV0) -> done! see http://www.ps3devwiki.com/wiki/Keys#lv0 | ||
=== Chain of trust Diagram 3.60++ === | === Chain of trust Diagram 3.60++ === | ||
<table width="100%" align="left"><tr><td align="left">[[File:Ps3-cryptochain-360.png|800px|thumb|left|LV0 with encapsulated loaders (appldr, isoldr, lv1ldr, lv2ldr).)]]</tr></ | <table width="100%" align="left"><tr><td align="left">[[File:Ps3-cryptochain-360.png|800px|thumb|left|LV0 with encapsulated loaders (appldr, isoldr, lv1ldr, lv2ldr).)]]</tr></tr></table><br /> | ||