Editing CXD9208GP

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| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
|-
|-
| data-sort-value="A04" | A4 || {{cellcolors|#8f8}} SIF_WRAC || SIF_WRAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B23 (write ?)
| data-sort-value="A04" | A4 || {{cellcolors|#8f8}} SIF_WRAC || SIF_WRAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B23
|-
|-
| data-sort-value="A05" | A5 || {{cellcolors|#8f8}} SIF_DACK || SIF_DACK_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A25
| data-sort-value="A05" | A5 || {{cellcolors|#8f8}} SIF_DACK || SIF_DACK_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A25
Line 25: Line 25:
| data-sort-value="A06" | A6 || {{cellcolors|#8f8}} SIF_DREQ0 || SIF_DREQ0_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B24
| data-sort-value="A06" | A6 || {{cellcolors|#8f8}} SIF_DREQ0 || SIF_DREQ0_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B24
|-
|-
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23 (read ?)
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23
|-
|-
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#afa}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#afa}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
Line 51: Line 51:
| data-sort-value="B04" | B4 || {{cellcolors|#8f8}} SIF_SINT || SINT_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C21
| data-sort-value="B04" | B4 || {{cellcolors|#8f8}} SIF_SINT || SINT_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C21
|-
|-
| data-sort-value="B05" | B5 || {{cellcolors|#6b6}} SIF_BE3 || SIF_BE3_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C24
| data-sort-value="B05" | B5 || {{cellcolors|#8f8}} SIF_BE3 || SIF_BE3_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C24
|-
|-
| data-sort-value="B06" | B6 || {{cellcolors|#8f8}} SIF_DREQ1 || SIF_DREQ1_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A24
| data-sort-value="B06" | B6 || {{cellcolors|#8f8}} SIF_DREQ1 || SIF_DREQ1_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A24
Line 57: Line 57:
| data-sort-value="B07" | B7 || {{cellcolors|#8f8}} SIF_RDY || SIF_RDY_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A22
| data-sort-value="B07" | B7 || {{cellcolors|#8f8}} SIF_RDY || SIF_RDY_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A22
|-
|-
| data-sort-value="B08" | B8 || {{cellcolors|#6b6}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
| data-sort-value="B08" | B8 || {{cellcolors|#8f8}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
|-
|-
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#afa}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#afa}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
Line 83: Line 83:
| data-sort-value="C05" | C5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C05" | C5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="C06" | C6 || {{cellcolors|#6b6}} SIF_BE0 || SIF_BE0_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B22
| data-sort-value="C06" | C6 || {{cellcolors|#8f8}} SIF_BE0 || SIF_BE0_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B22
|-
|-
| data-sort-value="C07" | C7 || {{cellcolors|#6b6}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
| data-sort-value="C07" | C7 || {{cellcolors|#8f8}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
|-
|-
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#afa}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#afa}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
Line 357: Line 357:
| data-sort-value="M07" | M7 || {{cellcolors|#99f}} PCI_TRDY || BC_PCI_TRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT25
| data-sort-value="M07" | M7 || {{cellcolors|#99f}} PCI_TRDY || BC_PCI_TRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT25
|-
|-
| data-sort-value="M08" | M8 || {{cellcolors|#77f}} PCI_CBE0 || BC_PCI_CBE0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP19
| data-sort-value="M08" | M8 || {{cellcolors|#99f}} PCI_CBE0 || BC_PCI_CBE0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP19
|-
|-
| data-sort-value="M09" | M9 || {{cellcolors|#99f}} PCI_FRAME || BC_PCI_FRAME || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT26
| data-sort-value="M09" | M9 || {{cellcolors|#99f}} PCI_FRAME || BC_PCI_FRAME || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT26
Line 381: Line 381:
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#bbf}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#bbf}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
|-
|-
| data-sort-value="N05" | N5 || {{cellcolors|#99f|#a00}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24 (system error)
| data-sort-value="N05" | N5 || {{cellcolors|#99f}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24
|-
|-
| data-sort-value="N06" | N6 || {{cellcolors|#99f}} PCI_DEVSEL || BC_PCI_DEVSEL || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU25
| data-sort-value="N06" | N6 || {{cellcolors|#99f}} PCI_DEVSEL || BC_PCI_DEVSEL || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU25
|-
|-
| data-sort-value="N07" | N7 || {{cellcolors|#77f}} PCI_CBE2 || BC_PCI_CBE2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP20
| data-sort-value="N07" | N7 || {{cellcolors|#99f}} PCI_CBE2 || BC_PCI_CBE2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP20
|-
|-
| data-sort-value="N08" | N8 || {{cellcolors|#99f}} PCI_GNT || BC_PCI_GNT1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN24
| data-sort-value="N08" | N8 || {{cellcolors|#99f}} PCI_GNT || BC_PCI_GNT1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN24
Line 409: Line 409:
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
|-
|-
| data-sort-value="P04" | P4 || {{cellcolors|#77f}} PCI_CBE1 || BC_PCI_CBE1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN19
| data-sort-value="P04" | P4 || {{cellcolors|#99f}} PCI_CBE1 || BC_PCI_CBE1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN19
|-
|-
| data-sort-value="P05" | P5 || {{cellcolors|#99f|#a00}} PCI_PERR || BC_PCI_PERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW25 (parity error)
| data-sort-value="P05" | P5 || {{cellcolors|#99f}} PCI_PERR || BC_PCI_PERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW25
|-
|-
| data-sort-value="P06" | P6 || {{cellcolors|#99f}} PCI_IRDY || BC_PCI_IRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU26
| data-sort-value="P06" | P6 || {{cellcolors|#99f}} PCI_IRDY || BC_PCI_IRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU26
|-
|-
| data-sort-value="P07" | P7 || {{cellcolors|#77f}} PCI_CBE3 || BC_PCI_CBE3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN20
| data-sort-value="P07" | P7 || {{cellcolors|#99f}} PCI_CBE3 || BC_PCI_CBE3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN20
|-
|-
| data-sort-value="P08" | P8 || {{cellcolors|#99f}} PCI_REQ || BC_PCI_REQ1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN22
| data-sort-value="P08" | P8 || {{cellcolors|#99f}} PCI_REQ || BC_PCI_REQ1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN22
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