Editing Documented SPU Channels

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|MFC LS Address
|MFC LS Address
|0x10  
|0x10  
|
|-
|SPU Read State Save-and-Restore
|0x0F
|
|-
|SPU Write State Save-and-Restore
|0x0E
|
|-
|SPU Read Machine Status
|0x0D
|
|
|-
|-
|MFC Read Tag Group Query Mask Channel
|MFC Read Tag Group Query Mask Channel
|0x0C
|0xC
|
|-
|SPU Read Event Mask
|0x0B
|
|-
|MFC Write Multisource Synchronization Request
|0x09
|
|-
|SPU Read Decrementer
|0x08
|
|-
|SPU Write Decrementer
|0x07
|
|
|-
|-
|SPU Signal Notification 2
|SPU Signal Notification 2
|0x04
|0x4
|
|
|-
|-
|SPU Signal Notification 1
|SPU Signal Notification 1
|0x03
|0x3
|
|-
|SPU Write Event Acknowledgment
|0x02
|
|-
|SPU Write Event Mask
|0x01
|
|-
|SPU Read Event Status
|0x00
|
|
|-
|-
|}
|}
* The rest of the 64 channels are reserved.
* There is a total of 128 channels (some of them are [[Documented SPU Channels]] and some others are [[Undocumented SPU Channels]])
=== Resources ===
* http://www.ibm.com/developerworks/library/pa-celldmas/
: ''The MFC is discussed in Section 6 of [https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/1AEEE1270EA2776387257060006E61BA/$file/CBEA_v1.02_11Oct2007_pub.pdf Cell Broadband Engine Architecture V1.0], while the first 27 DMA channels are listed in the [http://www.diku.dk/~rehr/cell/docs/SPU_language_extensions_2.1.pdf SPU C/C++ Language Extensions V2.0]''
{{Development}}<noinclude>[[Category:Main]]</noinclude>
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