Editing Hardware Flashers:NAND pinout

Jump to navigation Jump to search
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then publish the changes below to finish undoing the edit.

Latest revision Your text
Line 1: Line 1:
= NAND Consoles =
[[Category:Hardware]]
These are the earliest revisions of the PS3 motherboards: [[CECHAxx|CECHA]]/[[COK-00x|COK-001]], [[CECHBxx|CECHB]]/[[COK-00x|COK-001]], [[CECHCxx|CECHC]]/[[COK-00x|COK-002]], [[CECHExx|CECHE]]/[[COK-00x|COK-002W]], [[CECHGxx|CECHG]]/[[SEM-00x|SEM-001]] and contain 2x NAND chips for a total of 256MB. These chips are interleaved which is controlled by a proprietary controller chip codenamed "[[Starship2]]" or SS2. This chip handles the interleaving and presents the NAND Chips to the [[South Bridge]] as a single large coherent flash over a proprietary EBUS.
 
== NAND Wiring ==
== NAND Wiring ==
Flashers for NAND based consoles ([[CECHAxx|CECHA]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx|CECHB]]/[[COK-00x#COK-001|COK-001]], [[CECHCxx|CECHC]]/[[COK-00x#COK-002|COK-002]], [[CECHDxx|CECHD]]/unreleased, [[CECHExx|CECHE]]/[[COK-00x#COK-002W|COK-002W]], [[CECHFxx|CECHF]]/unreleased, [[CECHGxx|CECHG]]/[[SEM-00x|SEM-001]]) are generaly wired directly to the pins of the NAND ('''you cannot use the testpoints!''' between [[Southbridge]] and [[Starship2]]), plus ground and Vcc. Alternatively, boardtraces (between [[Starship2]] and [[NAND]]) can be used.
Flashers for NAND based consoles ([[CECHAxx|CECHA]]/[[COK-00x#COK-001|COK-001]], [[CECHBxx|CECHB]]/[[COK-00x#COK-001|COK-001]], [[CECHCxx|CECHC]]/[[COK-00x#COK-002|COK-002]], [[CECHDxx|CECHD]]/unreleased, [[CECHExx|CECHE]]/[[COK-00x#COK-002W|COK-002W]], [[CECHFxx|CECHF]]/unreleased, [[CECHGxx|CECHG]]/[[SEM-00x|SEM-001]]) are generaly wired directly to the pins of the NAND ('''you cannot use the testpoints!'''), plus ground and Vcc. Alternatively, boardtraces can be used that lead to the NAND pins.


=== Which NAND is low/high? ===
== Which NAND is low/high? ==
* [[COK-00x#COK-001|COK-001]] :
* [[COK-00x#COK-001|COK-001]] :
** IC3802 LOW (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. next to [[Starship2]])
** IC3802 LOW (<abbr title="main componentside with SATA connector, CELL BE, RSX etc">main componentside</abbr> next to [[Starship2]])
** IC3803 HIGH (backside next to 60-pin BD ATA connector)  
** IC3803 HIGH (backside next to 60-pin BD ATA connector)  


* [[COK-00x#COK-002|COK-002]] + [[COK-00x#COK-002W|COK-002W]] :
* [[COK-00x#COK-002|COK-002]] + [[COK-00x#COK-002W|COK-002W]] :
** [[:File:CECHC NAND-IC3802.JPG|IC3802 LOW]] (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. between SATA connector and [[South Bridge]])
** [[:File:CECHC NAND-IC3802.JPG|IC3802 LOW]] (<abbr title="main componentside with SATA connector, CELL BE, RSX etc">main componentside</abbr> between SATA connector and [[South Bridge]])
** [[:File:CECHC-NAND-IC3803.JPG|IC3803 HIGH]] (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc. between SATA connector and [[Connectors#CN2401_12P|AV Multi connector]])
** [[:File:CECHC-NAND-IC3803.JPG|IC3803 HIGH]] (<abbr title="main componentside with SATA connector, CELL BE, RSX etc.">main componentside</abbr> between SATA connector and [[Connectors#CN2401_12P|AV Multi connector]])


* [[SEM-00x|SEM-001]] :
* [[SEM-00x|SEM-001]] :
** IC3802 LOW (backside)
** IC3802 LOW (backside)
** IC3803 HIGH (main componentside with SATA connector, [[CELL BE]], [[RSX]] etc.)
** IC3803 HIGH (main componentside with SATA connector, CELL BE, RSX etc.)
 
=== EBUS Interface Testpoints on NAND consoles ===
Simular as on the NOR based consoles, testpoints can be found on the back of the PCB. It seems these are from the EBUS between the [[South Bridge]] and the [[Starship2]]. Attempts have been made to document/trace these. Addresslines 0-17 and Datalines 0-15 as well as some controllines are documented but so far these ''could not be used to read/flash the console''.


=== TriState on NAND consoles ===
using [[Starship2]] to southbridge /SB_EBUS_ACK @ SB_MAIN(P30)  (numbered 52 in [[:File:SS2_NOR.JPG]])
* CECHA (COK-001): IC3801:CXD4302GB-T6 pin:C1/ ebus jl:9308 (page 20 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])
* CECHC + CECHE (COK-002): IC3801:CXD4302GB-T6 pin:C1/ ebus jl:9308 (page 20 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])
* CECHG (SEM001): IC3801:CXD9909GB pin:C1/ ebus jl:9308 (page 21 of [https://web.archive.org/web/*/http://ps3devwiki.com/files/documents/-PS3%20Service%20Manuals/ servicemanual])


=== NAND Pinout table ===
== NAND Pinout table ==
{{NAND-Flashertable}}
{{NAND-Flashertable}}


== Structure ==
There are 2 NAND used, interleaved at 512byte/sector level, giving it a 1024 byte "interleaved sector". Pages are 2kb on each NAND.


{{Hardware Flashers}}


{{Hardware Flashers}}<noinclude>[[Category:Main]]</noinclude>
[[Category:Hardware Flashers]]
Please note that all contributions to PS3 Developer wiki are considered to be released under the GNU Free Documentation License 1.2 (see PS3 Developer wiki:Copyrights for details). If you do not want your writing to be edited mercilessly and redistributed at will, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource. Do not submit copyrighted work without permission!

To protect the wiki against automated edit spam, we kindly ask you to solve the following hCaptcha:

Cancel Editing help (opens in new window)