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===ps2_netemu.self===
===ps2_netemu.self===
Support for USB devices seems to be limited comparing to other available emulators. Although PS2 side of USB subsystem seems to be fully implemented. IOP emulator in SPU handle USB HW registers addresses and generate interrupt for PPU which later handle RW to mentioned registers in similar fashion to ps2_emu/ps2_gxemu. PS2 side of things can be disabled/enabled using one byte, when disabled USB writes are ignored, and USB reads return 0. Initial state is unknown. Emulator seems to accept HID controllers and use them as DS3.
<br/><br/>
Supported devices:
#BD Remote Control
#BD Remote Control
#PLAYSTATION(R)3 Controller (Vendor ID 0x54C, Product ID 0x268),  
#PLAYSTATION(R)3 Controller (Vendor ID 0x54C, Product ID 0x268),  
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Vector at 0xC00 address.
Vector at 0xC00 address.
  0x00 -
  0x00 -
       0 = return ((unk from 0x1C30/0x1C38 << 56) | thread_number << 48 | ctrl_CT1 (in bit 30) | srr1_EE (in bit 15) | srr1_PS (in bit 14) | srr1_DR (in bit 4))
       0 = exec smth,  
          Where 0x1C30/0x1C38 is selected depending on current HW thread.
          Thread number is current SW thread
          ctrl_CT1 is lower bit of CT (Current Thread) from PPC Control Register (0 for HW0, 1 for HW1)
          srr1_EE is MSR Enable External Interrupts bit from time when exception occurred (from before syscall was executed)
          srr1_PS is MSR Problem State bit from time when exception occurred (from before syscall was executed)
          srr1_DR is MSR Data Relocate bit from time when exception occurred (from before syscall was executed)
       1 = 0x132 lv1 panic
       1 = 0x132 lv1 panic
       2 = 0x133 lv1 panic
       2 = 0x133 lv1 panic
Line 1,498: Line 1,489:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#fff|#000}} Skip r5900 CACHE IXIN/IHIN opcodes
! {{cellcolors|#fff|#000}} Switch something
| 0x02 || 0x02 || 0x03
| 0x02 || 0x02 || 0x03
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
Line 1,508: Line 1,499:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#bd5|#000}} Alternative VIF1 DIRECT/DIRECTHL handler
! {{cellcolors|#bd5|#000}} Set DIRECT/DIRECTHL VIF1 in SP3 EEDMA
| 0x04 || 0x04 || {{cellcolors|#eee|#b44|center}} <abbr style="cursor:help; text-decoration:none" title="Not Available">0x05</abbr>
| 0x04 || 0x04 || {{cellcolors|#eee|#b44|center}} <abbr style="cursor:help; text-decoration:none" title="Not Available">0x05</abbr>
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#fff|#000}} Alternative VIF1 OFFSET handler
! {{cellcolors|#fff|#000}} Switch something
| 0x05 || 0x05 || 0x06
| 0x05 || 0x05 || 0x06
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#c96|#000}} Delay VU1 xgkick by X cycles
! {{cellcolors|#c96|#000}} Delay VU xgkick by X cycles
| 0x06 || 0x06 || 0x07
| 0x06 || 0x06 || 0x07
| 1 || style="text-align:left" | uint32_t
| 1 || style="text-align:left" | uint32_t
| colspan="3" {{cellcolors|#c96|#000|center}} <abbr title="2=2cycles, 4=4cycles, 8=8cycles">cycles</abbr>
| colspan="3" {{cellcolors|#c96|#000|center}} <abbr title="2=2cycles, 4=4cycles, 8=8cycles">cycles</abbr>
|-
|-
! {{cellcolors|#c96|#000}} Patch VU1 memory by <abbr title="two bit masks for original and patched data">bitmask</abbr>
! {{cellcolors|#c96|#000}} Patch VU memory by <abbr title="two bit masks for original and patched data">bitmask</abbr>
| 0x07 || 0x07 || 0x08
| 0x07 || 0x07 || 0x08
| 3 || style="text-align:left" | 8&nbsp;*&nbsp;uint32_t
| 3 || style="text-align:left" | 8&nbsp;*&nbsp;uint32_t
| colspan="3" {{cellcolors|#c96|#000|center}} <abbr title="read mask, read mask, original opcode, original opcode, write mask, write mask, replace opcode, replace opcode">MASK</abbr>
| colspan="3" {{cellcolors|#c96|#000|center}} <abbr title="read mask, read mask, original opcode, original opcode, write mask, write mask, replace opcode, replace opcode">MASK</abbr>
|-
|-
! {{cellcolors|#9f9|#000}} Patch EE memory 64 bit
! {{cellcolors|#9f9|#000}} Patch EE memory with 2 opcodes
| 0x08 || 0x08 || 0x09
| 0x08 || 0x08 || 0x09
| <abbr title="command">1</abbr>→<abbr title="list">32</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
| <abbr title="command">1</abbr>→<abbr title="list">32</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
| {{cellcolors|#9f9|#000|center}} <abbr title="amount of patches in the LIST">count</abbr> || colspan="2" {{cellcolors|#9f9|#000|center}} <abbr title="offset, original opcode, original opcode, replace opcode, replace opcode">LIST</abbr>
| {{cellcolors|#9f9|#000|center}} <abbr title="amount of patches in the LIST">count</abbr> || colspan="2" {{cellcolors|#9f9|#000|center}} <abbr title="offset, original opcode, original opcode, replace opcode, replace opcode">LIST</abbr>
|-
|-
! {{cellcolors|#9f9|#000}} Patch EE memory 32 bit
! {{cellcolors|#9f9|#000}} Patch EE memory with 1 opcode
| {{NA}} || {{NA}} || 0x0A
| {{NA}} || {{NA}} || 0x0A
| <abbr title="command">1</abbr>→<abbr title="list">32</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
| <abbr title="command">1</abbr>→<abbr title="list">32</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
Line 1,563: Line 1,554:
| {{cellcolors|#f93|#000|center}} <abbr title="min 0x100000">start&nbsp;offset</abbr> || colspan="2" {{cellcolors|#f93|#000|center}} <abbr title="max 0x1FFFFFFF">end&nbsp;offset</abbr>
| {{cellcolors|#f93|#000|center}} <abbr title="min 0x100000">start&nbsp;offset</abbr> || colspan="2" {{cellcolors|#f93|#000|center}} <abbr title="max 0x1FFFFFFF">end&nbsp;offset</abbr>
|-
|-
! {{cellcolors|#f93|#000}} FPU accurate MUL/DIV range
! {{cellcolors|#f93|#000}} COP2 accurate MUL/DIV range
| 0x0E || 0x0E || 0x10
| 0x0E || 0x0E || 0x10
| 32 || style="text-align:left" | 2&nbsp;*&nbsp;uint32_t
| 32 || style="text-align:left" | 2&nbsp;*&nbsp;uint32_t
Line 1,573: Line 1,564:
| colspan="3" {{cellcolors|#f93|#000|center}} <abbr title="min 0x000, max 0xFF8">offset</abbr>
| colspan="3" {{cellcolors|#f93|#000|center}} <abbr title="min 0x000, max 0xFF8">offset</abbr>
|-
|-
! {{cellcolors|#588|#fff}} VU0/COP2 multi cmd
! {{cellcolors|#588|#fff}} VU related ?
| 0x10 || 0x10 || 0x12
| 0x10 || 0x10 || 0x12
| <abbr title="command">1</abbr>→<abbr title="list">63</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
| <abbr title="command">1</abbr>→<abbr title="list">63</abbr> || style="text-align:left" | uint32_t&nbsp;+&nbsp;LIST
Line 1,583: Line 1,574:
| colspan="3" {{cellcolors|#dda|#000|center}} time ?
| colspan="3" {{cellcolors|#dda|#000|center}} time ?
|-
|-
! {{cellcolors|#f93|#000}} Alternative VU1 ADD/SUB
! {{cellcolors|#f93|#000}} VU1 transform ADD/SUB
| 0x12 || 0x12 || 0x14
| 0x12 || 0x12 || 0x14
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#fff|#000}} Patch IOP SPE program
! {{cellcolors|#fff|#000}} Set something with bit flags
| 0x13 || 0x13 || 0x15
| 0x13 || 0x13 || 0x15
| 1 || style="text-align:left" | uint32_t
| 1 || style="text-align:left" | uint32_t
| colspan="3" | 2 or higher
| colspan="3" | ?
|-
|-
! {{cellcolors|#fff|#000}} Unknown
! {{cellcolors|#fff|#000}} Unknown
Line 1,598: Line 1,589:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#9cf|#000}} Alternative COP0 MTC0/MFC0 Count ($9) handler
! {{cellcolors|#9cf|#000}} COP0 configure MTC0/MFC0
| 0x15 || 0x15 || 0x17
| 0x15 || 0x15 || 0x17
| 1 || style="text-align:left" | uint8_t ?
| 1 || style="text-align:left" | uint8_t ?
Line 1,613: Line 1,604:
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#fff|#000}} End fromIPU DMA transfer on BCLR command
! {{cellcolors|#fff|#000}} Switch something
| 0x17 || 0x18 || 0x1A
| 0x17 || 0x18 || 0x1A
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#fff|#000}} IPU IDEC Hack
! {{cellcolors|#fff|#000}} Switch something
| 0x18 || 0x19 || 0x1B
| 0x18 || 0x19 || 0x1B
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
Line 1,638: Line 1,629:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#fff|#000}} Enable VIF0 cmds MSXXX/MPG/FLUSHE timings.
! {{cellcolors|#fff|#000}} Set something
| 0x1C || 0x1C || 0x1F
| 0x1C || 0x1C || 0x1F
| 1 || style="text-align:left" | uint32_t
| 1 || style="text-align:left" | uint32_t
| colspan="3" | Initial cycles to run
| colspan="3" | ?
|-
|-
! {{cellcolors|#fff|#000}} Set something
! {{cellcolors|#fff|#000}} Set something
Line 1,658: Line 1,649:
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#fff|#000}} Snowblind Engine hack
! {{cellcolors|#fff|#000}} Switch something
| 0x1F || 0x20 || 0x23
| 0x1F || 0x20 || 0x23
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#ddf|#000}} SIO2 Delay
! {{cellcolors|#ddf|#000}} Internal image aspect ratio ?
| 0x20 || 0x21 || 0x24
| 0x20 || 0x21 || 0x24
| 1 || style="text-align:left" | uint64_t
| 1 || style="text-align:left" | uint64_t
Line 1,688: Line 1,679:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#aaf|#000}} CDVD seek timing
! {{cellcolors|#aaf|#000}} CDVD read/seek timings ?
| 0x25 || 0x26? || 0x29
| 0x25 || 0x26? || 0x29
| 1 || style="text-align:left" | 2&nbsp;*&nbsp;uint32_t
| 1 || style="text-align:left" | 2&nbsp;*&nbsp;uint32_t
Line 1,698: Line 1,689:
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
| colspan="3" {{cellcolors|#ddd|#666|center}} ''Nothing''
|-
|-
! {{cellcolors|#aaf|#000}} Enable CDDA hack <abbr title="PS2 MECHACON related">(CDVD)</abbr>
! {{cellcolors|#aaf|#000}} Switch something <abbr title="PS2 MECHACON related">(CDVD)</abbr>
| 0x27? || 0x28 || 0x2B
| 0x27? || 0x28 || 0x2B
| 1 || style="text-align:left" | 0
| 1 || style="text-align:left" | 0
Line 1,718: Line 1,709:
| colspan="3" | ?
| colspan="3" | ?
|-
|-
! {{cellcolors|#fff|#000}} SPU2 multi cmd.
! {{cellcolors|#fff|#000}} Set something
| 0x2B || {{NA}} || 0x2F
| 0x2B || {{NA}} || 0x2F
| 1 || style="text-align:left" | uint32_t
| 1 || style="text-align:left" | uint32_t
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