Editing Syscon SPI

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= Overview =
= Overview =
[[Syscon Hardware|Syscon]] has multiple SPI busses for communicating with different hardware peripherals:
Syscon has multiple SPI busses for communicating with different hardware peripherals:
* [[CELL BE]]
* Cell BE
* [[RSX]]
* RSX
* [[South Bridge]]
* Southbridge
* Syscon internal [[SC EEPROM|EEPROM]] (only in [[Mullion]]) data bus in between syscon EEPROM and a service connector


= Cell BE SPI =
= Cell BE SPI =
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== SPI Protocol ==
== SPI Protocol ==
* Fixed size header
* Fixed size header
   * 8-bit [[Syscon SPI#SPI Command ID|Command ID]]
   * 8-bit Command ID
   * 16-bit SPI address
   * 16-bit SPI address
* Register-specific data length
* Register-specific data length
* A quick and dirty DSView decoder is available here: [https://github.com/MikeM64/ps3_sc_spi ps3_sc_spi]


=== SPI Command ID ===
=== SPI Command ID ===
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|-
|-
| 0x9104 || 0x24000509104 || Unknown || 32 || Written after every Syscon packet transfer
| 0x9104 || 0x24000509104 || Unknown || 32 || Written after every Syscon packet transfer
|-
| 0xa000 || 0x2400008c000 || SC -> BE packet buffer || 32768 (0x1000 '''bytes''') || Buffer where Cell reads packets from Syscon. Can write to this buffer over the SPI bus.
|-
| 0xb000 || 0x2400008d000 || BE -> SC packet buffer || 32768 (0x1000 '''bytes''') || Buffer where Syscon reads packets from Cell. Can NOT be written over the SPI bus. This is most likely held within SC.
|-
| N/A || 0x2400008e100 || Syscon packet doorbell || 32 || Will assert the SB_INT line when 0x1 is written to it from the Cell
|}
|}


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= Southbridge SPI =
= Southbridge SPI =
To be discovered...
To be discovered...
{{Reverse engineering}}<noinclude>[[Category:Main]]</noinclude>
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