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• Template:In5
  -- NOTE N3: The nesting level of this template is only 2 levels
  3 KB (364 words) - 22:18, 14 December 2012
• CXD4302GB
  | N3 || FD1[12] ||
  13 KB (1,741 words) - 01:38, 18 July 2017
• EBUS
  | 60 || - || IOR || /SB_BUS_IOR (EBUSIORZ / N3) || || ||
  11 KB (1,424 words) - 15:11, 14 August 2021
• CXD2984GB
  | N3 || ||
  23 KB (2,836 words) - 22:07, 6 June 2022
• CXD9208GP
  | data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected
  34 KB (4,383 words) - 13:03, 20 October 2022
• HV Syscall Reference
  status = lv1_create_repository_node(/*IN*/ n1, n2, n3, n4, v1, v2 ); status = lv1_get_repository_node_value(/*IN*/ lpar_id, n1, n2, n3, n4 /*OUT*/ &v1, &v2 );
  114 KB (17,459 words) - 09:10, 3 October 2022
• CXD9963GB
  | data-sort-value="0N03" | N3 || || || ||
  42 KB (4,184 words) - 15:18, 19 November 2022
• Template:Syscon pinout BGA 200 pads
  | data-sort-value="N03" | N3 || data-sort-value="ZNA" {{cellcolors|#eee|#888}} N/A || data-sort-value="Z
  50 KB (6,366 words) - 03:43, 16 November 2022
• Template:RSX pad layout 41x41
  | N3 || ||
  44 KB (5,008 words) - 17:08, 30 September 2022
• Template:CELL pad layout 45nm v1
  | data-sort-value="0N03" | N3 || || || ||
  72 KB (5,997 words) - 05:38, 16 November 2022
• Template:CELL pad layout 45nm v2
  | data-sort-value="0N03" | N3 || || || ||
  74 KB (6,188 words) - 05:39, 16 November 2022
• Template:CELL pad layout 65nm
  | data-sort-value="0N03" | N3 || || || ||
  73 KB (6,284 words) - 05:37, 16 November 2022
• Hypervisor Reverse Engineering
  unsigned long long n3, h = ((((n1 ^ n4) >> 32) ^ (n2 ^ n3)) ^ (((n2 ^ n3) >> 32) ^ (n1 ^ n4))) & ~0xC0000000ULL;
  267 KB (38,289 words) - 07:26, 20 August 2021
• Template:CELL pad layout 90nm
  | data-sort-value="0N03" | N3 || Y0_DQ2_4 || Y0_XDR0_DQ11 || {{pino}} || Connected to [[RAM|XDR DRAM]] Y0
  351 KB (42,654 words) - 05:34, 16 November 2022