CPU: Difference between revisions

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[[Category:Hardware]]
When you think about it, that's got to be the right anwesr.
== 4 core ARM Cortex-A9 MPCore ==
 
The ARM Cortex-A9 MPCore is a multicore processor providing up to 4 cache-coherent Cortex-A9 cores, each implementing the ARM v7 instruction set architecture.
 
=== Specifications ===
* Designed by: ARM
* Common manufacturer(s): TSMC
* CPU clock rate: 800 MHz to 2000 MHz (generic spec, needs confirmation on Vita platform)
* Instruction set: ARMv7
* Cores: 1-4
* L1 cache: 32 kB I/32 kB D
* L2 cache controller: (0-4 MB)
 
=== Debugging/Tracing ===
CoreSight for Cortex-A series processors enable developers to control (debug) and observe (trace) their Cortex-A processor-based SoC with fewer pins. Cortex-A processor debug and run time control can be performed with only 2 pins using the Serial Wire Debug technology or alternatively using JTAG, when highly compressed real-time trace of the cores and others system trace can be captured on-chip (ETB) or exported through a dedicated trace port (TPIU).
 
== External References ==
* [http://www.arm.com/products/processors/cortex-a/cortex-a9.php ARM Cortex-A9 Processor - main page]
** [http://www.arm.com/files/pdf/ARMCortexA-9Processors.pdf White paper - The ARM Cortex-A9 Processors]
** [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0407e/index.html Cortex-A9 MPCore Technical Reference Manual]
* [http://www.arm.com/products/system-ip/debug-trace/coresight-soc-components/index.php CoreSight - main page]
** [http://www.arm.com/products/system-ip/debug-trace/coresight-soc-components/serial-wire-debug.php CoreSight Debug Access Port : Serial Wire Debug]

Revision as of 18:49, 17 December 2011

When you think about it, that's got to be the right anwesr.

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