CXD9208GP: Difference between revisions

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(→‎Pinout: "Pad" table column sorting corrections)
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PS2 bridge located in between EE+GS and the [[South Bridge]]
PS2 bridge located in between EE+GS and the [[South Bridge]]


== Pinout ==
<includeonly><br style="clear: both;" />
{| class="wikitable mw-datatable sortable" style="width:100%; line-height:1em; font-size:0.85em"
<span style="font-size:175%; font-family:Times New Roman;">Pinout</span>
|+
----
! style="border-bottom:hidden; padding:2px" | Pad !! colspan="2" | Name !! style="border-bottom:hidden; padding:2px" | Type !! style="border-bottom:hidden" | Description
</includeonly><div style="float:right">[[File:CXR713120-201GB-bottom.JPG|300px|thumbnail|right|[[Mullion]] syscons, bottom view<br>With pad A1 mark at south-east corner]]<br>[[File:CXR714120-301GB - Top.jpg|300px|thumbnail|right|[[Mullion]] syscon, top view<br>With pad A1 mark at south-west corner]]</div>
|-
 
! style="border-top:hidden; padding:0px; background-position:50%" | !! style="width:25px; min-width:25px; padding-right:0px" | Internal !! style="width:25px; min-width:25px; padding-right:0px" | External !! style="border-top:hidden; background-position:50%" | !! style="border-top:hidden; background-position:50%" |  
<div style="overflow:auto; <includeonly>height:800px;</includeonly>">
 
{|class="wikitable sortable" style="width:100%; line-height:120%; font-size:90%"
|+ {{captionlinks|Syscon pinout BGA 200 pads}}
|-
|-
| data-sort-value="A01" | A1 || {{cellcolors|#333|#fff}} TEST_IN_0 || GND || {{pin}} || style="color:#888" | Ground
! Pad !! Name !! Port !! Description
|-
|-
| data-sort-value="A02" | A2 || {{cellcolors|#333|#fff}} PLLAVS1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="T02" | T2 || BE_INT || rowspan="9" | M || Connected to CELL 90nm pad AW19
|-
|-
| data-sort-value="A03" | A3 || {{cellcolors|#8f8}} SIF_MSCLK || MSCLK || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pads B8 and A21
| data-sort-value="R01" | R1 || PM7 ||
|-
|-
| data-sort-value="A04" | A4 || {{cellcolors|#8f8}} SIF_WRAC || SIF_WRAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B23 (write ?)
| data-sort-value="R02" | R2 || PM6 ||
|-
|-
| data-sort-value="A05" | A5 || {{cellcolors|#8f8}} SIF_DACK || SIF_DACK_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A25
| data-sort-value="P01" | P1 || BE_POWGOOD || Connected to CELL 90nm pad AV20
|-
|-
| data-sort-value="A06" | A6 || {{cellcolors|#8f8}} SIF_DREQ0 || SIF_DREQ0_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B24
| data-sort-value="P02" | P2 || BE_RESET || Connected to CELL 90nm pad AW20
|-
|-
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23 (read ?)
| data-sort-value="N01" | N1 || BE_SPI_CLK || Connected to CELL 90nm pad AY13 (SPI Bus)
|-
|-
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#afa}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
| data-sort-value="N02" | N2 || BE_SPI_DO || Connected to CELL 90nm pad AV13 (SPI Bus)
|-
|-
| data-sort-value="A09" | A9 || data-sort-value="SIF_AD07" {{cellcolors|#afa}} SIF_AD7 || data-sort-value="SIF_BC_AD07" | SIF_BC_AD7 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C18
| data-sort-value="M01" | M1 || BE_SPI_DI || Connected to CELL 90nm pad AR13 (SPI Bus)
|-
|-
| data-sort-value="A10" | A10 || data-sort-value="SIF_AD09" {{cellcolors|#afa}} SIF_AD9 || data-sort-value="SIF_BC_AD09" | SIF_BC_AD9 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B18
| data-sort-value="M02" | M2 || BE_SPI_CS || Connected to CELL 90nm pad AP13 (SPI Bus)
|-
|-
| data-sort-value="A11" | A11 || {{cellcolors|#afa}} SIF_AD18 || SIF_BC_AD18 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A12
| data-sort-value="L04" | L4 || PL8 || rowspan="9" | L<!--the name "Port N" used here is an official typo--> || rowspan="9" | unused
|-
|-
| data-sort-value="A12" | A12 || {{cellcolors|#afa}} SIF_AD21 || SIF_BC_AD21 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C11
| data-sort-value="L05" | L5 || PL7
|-
|-
| data-sort-value="A13" | A13 || {{cellcolors|#afa}} SIF_AD29 || SIF_BC_AD29 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B9
| data-sort-value="K04" | K4 || PL6
|-
|-
| data-sort-value="A14" | A14 || data-sort-value="SIF_AD06" {{cellcolors|#afa}} SIF_AD6 || data-sort-value="SIF_BC_AD06" | SIF_BC_AD6 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A18
| data-sort-value="K05" | K5 || PL5
|-
|-
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |
| data-sort-value="J04" | J4 || PL4
|-
|-
| data-sort-value="B01" | B1 || {{cellcolors|#eee|#888}} GPIO33_6 || CL7307 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="J05" | J5 || PL3
|-
|-
| data-sort-value="B02" | B2 || {{cellcolors|#eee|#888}} GPIO33_5 || CL7302 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="H04" | H4 || PL2
|-
|-
| data-sort-value="B03" | B3 || {{cellcolors|#e63|#fff}} PLLAVD1 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="H05" | H5 || PL1
|-
|-
| data-sort-value="B04" | B4 || {{cellcolors|#8f8}} SIF_SINT || SINT_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C21
| data-sort-value="H06" | H6 || PL0
|-
|-
| data-sort-value="B05" | B5 || {{cellcolors|#6b6}} SIF_BE3 || SIF_BE3_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C24
| data-sort-value="A08" | A8 || SB_SPI_CLK || rowspan="8" | K || rowspan="4" | Southbridge SPI Bus
|-
|-
| data-sort-value="B06" | B6 || {{cellcolors|#8f8}} SIF_DREQ1 || SIF_DREQ1_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A24
| data-sort-value="B08" | B8 || SB_SPI_DO
|-
|-
| data-sort-value="B07" | B7 || {{cellcolors|#8f8}} SIF_RDY || SIF_RDY_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A22
| data-sort-value="A09" | A9 || SB_SPI_DI
|-
|-
| data-sort-value="B08" | B8 || {{cellcolors|#6b6}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
| data-sort-value="B09" | B9 || SB_SPI_CS
|-
|-
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#afa}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
| data-sort-value="A10" | A10 || DVE_I2C_SCL || Connected to Digital Video Encoder [[CXM4024R]] pin 35
|-
|-
| data-sort-value="B10" | B10 || data-sort-value="SIF_AD03" {{cellcolors|#afa}} SIF_AD3 || data-sort-value="SIF_BC_AD03" | SIF_BC_AD3 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C19
| data-sort-value="B10" | B10 || DVE_I2C_SDA || Connected to Digital Video Encoder [[CXM4024R]] pin 36
|-
|-
| data-sort-value="B11" | B11 || {{cellcolors|#afa}} SIF_AD20 || SIF_BC_AD20 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A11
| data-sort-value="A11" | A11 || ACDC_STBY || Connected to [[Power Supply]] (small connector). This signal enables +12V_MAIN power rail (big prongs)
|-
|-
| data-sort-value="B12" | B12 || {{cellcolors|#afa}} SIF_AD30 || SIF_BC_AD30 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C9
| data-sort-value="B11" | B11 || PK0 ||
|-
|-
| data-sort-value="B13" | B13 || {{cellcolors|#afa}} SIF_AD26 || SIF_BC_AD26 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A9
| data-sort-value="B05" | B5 || DVE_RST || rowspan="8" | J || Connected to Digital Video Encoder [[CXM4024R]] pin 31 ?
|-
|-
| data-sort-value="B14" | B14 || {{cellcolors|#afa}} SIF_AD11 || SIF_BC_AD11 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C15
| data-sort-value="A05" | A5 || DISC_OUT12_SW || Connected to BluRay Drive connector (CN3221) pin 58
|-
|-
| data-sort-value="B99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="B02" | B2 || DISC_OUT8_SW || Connected to BluRay Drive connector (CN3221) pin 57
|-
|-
| data-sort-value="C01" | C1 || {{cellcolors|#bbf}} PCI_AD30 || BC_PCI_AD30 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU31
| data-sort-value="A02" | A2 || DISC_IN || Connected to BluRay Drive connector (CN3221) pin 52
|-
|-
| data-sort-value="C02" | C2 || {{cellcolors|#bbf}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
| data-sort-value="B03" | B3 || PJ3 || Not connected in retail PS3 models (testpad CL4089)
|-
|-
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A03" | A3 || SW_0 || Connected to [[Regulators#Fujitsu_MB39A116PFT_.282_channel_DC.2FDC_converter.29 | Fujitsu MB39A116PFT]] (IC6003) pin 9 (switches +5V_MISC)<br>Connected to [[Regulators#Fujitsu_MB39A116PFT_.282_channel_DC.2FDC_converter.29 | Fujitsu MB39A116PFT]] (IC6003) pin 10 (switches +3.3V_MISC)<br>Connected to [[Components#Texas_Instruments_SN105233DBTR|Texas Instruments SN105233DBTR]] (IC6301) pin 10 (switches +1.7_MISC)
|-
|-
| data-sort-value="C04" | C4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="B04" | B4 || SW_8_B || Connected to [[Regulators#Mitsumi_MM1561JFBE_.28Low-Saturation_500mA_Regulators.29|Mitsumi MM1561JFBE]] (IC2408) pin 5 (switches +1.8V_ANA)<br>Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29|Mitsumi MM1593DFBEG]] (IC2407) pin 5 (switches +3.3V_ANA)<br>Connected to transistor DTC144EUA-T106 (Q2401) base pin (switches +5V_ANA ?)<br>Connected to [[Regulators#OnSemi_NCP511SN15T1G_.281.5_V_150_mA_CMOS_Low_Iq_Low_Dropout_Voltage_Regulator_-_TSOP-5.29|OnSemi NCP511SN15T1G]] (IC6019) pin 3 (switches +1.5V_AVCG_VDDIO)<br>Connected to [[Regulators#Rohm_BD3521FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3521FVM-TR]] (IC6017) pin 3 (switches +1.5V_RSX_VDDIO)
|-
|-
| data-sort-value="C05" | C5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A04" | A4 || SW_8_C || Connected to [[Components#Texas_Instruments_SN105233DBTR|Texas Instruments SN105233DBTR]] (IC6301) pin 9 (switches +1.8V_RSX_FBVDDQ)<br>Connected to [[Regulators#OnSemi_NCP511SN18T1_.281.8V_150_mA_CMOS_Low_Iq_Low-Dropout_Voltage_Regulator.29 | OnSemi NCP511SN18T1]] (IC6008) pin 3 (switches +1.8V_RSX_PLL_VDD)
|-
|-
| data-sort-value="C06" | C6 || {{cellcolors|#6b6}} SIF_BE0 || SIF_BE0_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B22
| data-sort-value="L16" | L16 || SW_PCI || rowspan="6" | I || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 5 (switches +1.5V_BRIDGE) for the PS2 bridge [[CXD9208GP]]<br>Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 5 (switches +3.3V_BRIDGE) for the PS2 bridge [[CXD9208GP]]<br>Connected to PCI service connector pin 80
|-
|-
| data-sort-value="C07" | C7 || {{cellcolors|#6b6}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
| data-sort-value="L15" | L15 || DISC_CHUCK || Connected to BluRay Drive connector (CN3221) pin 54
|-
|-
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#afa}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
| data-sort-value="M16" | M16 || DISC_PHOT_LED || Connected to BluRay Drive connector (CN3221) pin 53
|-
|-
| data-sort-value="C09" | C9 || data-sort-value="SIF_AD00" {{cellcolors|#afa}} SIF_AD0 || data-sort-value="SIF_BC_AD00" | SIF_BC_AD0 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B19
| data-sort-value="M15" | M15 || SW_2 || Connected to [[Regulators#Texas_Instruments_TPS51117PWRG4_.281.8V_to_28V_Input_Sync._Step_Down_Controller_10A_0.75_V_to_5.5_V.29|Texas Instruments TPS51117PWRG4]] (IC6302) pin 1 (switches +1.8V_VDD_MEM)
|-
|-
| data-sort-value="C10" | C10 || {{cellcolors|#afa}} SIF_AD28 || SIF_BC_AD28 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B12
| data-sort-value="N16" | N16 || DIAG_MODE || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 13
|-
|-
| data-sort-value="C11" | C11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="N15" | N15 || BACKUP_MODE || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 14
|-
|-
| data-sort-value="C12" | C12 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E06" | E6 || HDMI_INT || rowspan="8" | H || Connected to [[TC7WP3125FK]] (IC2501) pin 6. This is a syscon input at 3.3V<br> The [[TC7WP3125FK]] converts the signal originally triggered by [[Sil9132CBU]] pad E10 ? at 1.5V and converts it to 3.3V for syscon<br>The [[TC7WP3125FK]] also converts the signal RS_SPDO0 (at 1.5V) into RS_SPDO0_33 (at 3.3V)
|-
|-
| data-sort-value="C13" | C13 || {{cellcolors|#afa}} SIF_AD31 || SIF_BC_AD31 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A8
| data-sort-value="D06" | D6 || VD_CECI0 ||
|-
|-
| data-sort-value="C14" | C14 || {{cellcolors|#afa}} SIF_AD15 || SIF_BC_AD15 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B15
| data-sort-value="E07" | E7 || MECHA_INT || Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163)
|-
|-
| data-sort-value="C99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="D07" | D7 || RSX_POW_FAIL<!--RS_POW_FAIL is an official typo, the name appears several times but only one of them have the typo--> || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 7
|-
|-
| data-sort-value="D01" | D1 || {{cellcolors|#bbf}} PCI_AD26 || BC_PCI_AD26 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU30
| data-sort-value="E08" | E8 || MUL_CHKSTP_IN || SB_CHKSTP_OUT
|-
|-
| data-sort-value="D02" | D2 || {{cellcolors|#bbf}} PCI_AD28 || BC_PCI_AD28 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW31
| data-sort-value="D08" | D8 || MUL_TRG_IN || Connected to missing components (IC4003, IC4004, IC4005) pin 3 and 6 (related with BE_TRG_IN/OUT, RSX_TRG_IN/OUT, SB_TRG_IN/OUT)
|-
|-
| data-sort-value="D03" | D3 || {{cellcolors|#bbf}} PCI_AD31 || BC_PCI_AD31 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT31
| data-sort-value="E09" | E9 || SYS_THR_ALRT || Connected to CELL 90nm pad AP23
|-
|-
| data-sort-value="D04" | D4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="D09" | D9 || SB_INT ||
|-
|-
| data-sort-value="D05" | D5 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="M11" | M11 || SW_ATA || rowspan="8" | G || Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)<br>Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)<br>Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD)
|-
|-
| data-sort-value="D06" | D6 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="N11" | N11 || SW_4_A || Connected to wifi board connector (CN3701) pin 9 (named 11G_PWR_EN). This is a syscon output<br>Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller)
|-
|-
| data-sort-value="D07" | D7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="M10" | M10 || XDR_FET_VREF || Connected to transistor DTC144EUA-T106 (Q4008). Switches XDR_RQ_VREF_FET
|-
|-
| data-sort-value="D08" | D8 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="N10" | N10 || XDR_FET_SCK || BE_RQ_SCK_BJT
|-
|-
| data-sort-value="D09" | D9 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="M09" | M9 || BUZZER ||
|-
|-
| data-sort-value="D10" | D10 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="N09" | N9 || SW_PWM || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 2
|-
|-
| data-sort-value="D11" | D11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="M08" | M8 || FANPWM1 || Secondary fan output (non-retail PS3 models only)
|-
|-
| data-sort-value="D12" | D12 || {{cellcolors|#afa}} SIF_AD10 || SIF_BC_AD10 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B16
| data-sort-value="N08" | N8 || FANPWM0 || Primary fan output (all PS3 models)
|-
|-
| data-sort-value="D13" | D13 || data-sort-value="SIF_AD05" {{cellcolors|#afa}} SIF_AD5 || data-sort-value="SIF_BC_AD05" | SIF_BC_AD5 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A17
| data-sort-value="E10" | E10 || MUL_CHKSTP_OUT || rowspan="8" | F ||
|-
|-
| data-sort-value="D14" | D14 || {{cellcolors|#afa}} SIF_AD14 || SIF_BC_AD14 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B14
| data-sort-value="D10" | D10 || MUL_TRG_OUT || Connected to missing components (IC4006) pin 2 (related with BE_TRG_IN/OUT, RSX_TRG_IN/OUT, SB_TRG_IN/OUT)
|-
|-
| data-sort-value="D99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="E11" | E11 || SB_CGRESET || SB_CGRST (the name indicates that it resets the clock generator for the southbridge)
|-
|-
| data-sort-value="E01" | E1 || {{cellcolors|#bbf}} PCI_AD25 || BC_PCI_AD25 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT29
| data-sort-value="D11" | D11 || SB_RESET || Connected to [[88SA8040-TBC1]] SATA2PATA BluRay controller pin 17<br>Connected to GL852 (IC3305) USB HUB pin 38<br>Connected to Multi-card-board connector CN3219 pin 7
|-
|-
| data-sort-value="E02" | E2 || {{cellcolors|#bbf}} PCI_AD27 || BC_PCI_AD27 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT30
| data-sort-value="E12" | E12 || BT_WAKEON || Connected to wifi board connector (CN3701) pin 30 (named BT_WAKE). This is a syscon input
|-
|-
| data-sort-value="E03" | E3 || {{cellcolors|#bbf}} PCI_AD24 || BC_PCI_AD24 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU29
| data-sort-value="D12" | D12 || PF2<br>BE_VCS_1.25_ON || [[COK-001]]/[[COK-002]] PF2 (Not connected)<br>[[SEM-001]] BE_VCS_1.25_ON
|-
|-
| data-sort-value="E04" | E4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E13" | E13 || PF1<br>BE_VCS_1.30_ON || [[COK-001]]/[[COK-002]] PF1 (Not connected)<br>[[SEM-001]] BE_VCS_1.30_ON
|-
|-
| data-sort-value="E05" | E5 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="D13" | D13 || SW_1_A || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29|Mitsumi MM1593DFBEG]] (IC6020) pin 5 (switches +3.3V_MK_VDD) for Clock Synthesizer
|-
|-
| data-sort-value="E06" | E6 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="A12" | A12 || EJECT_SW || rowspan="8" | E || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 5
|-
|-
| data-sort-value="E07" | E7 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="B12" | B12 || POW_SW || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 4
|-
|-
| data-sort-value="E08" | E8 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A13" | A13 || SB_EBUS_RESET || SS2_RESET (StarShip2 related), not connected because a missing resistor (R4135) ?
|-
|-
| data-sort-value="E09" | E9 || {{cellcolors|#333|#fff}} TEST_IN_3 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="B13" | B13 || SB_EBUS_BRDY || SS2_BRDY (StarShip2 related)
|-
|-
| data-sort-value="E10" | E10 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="A14" | A14 || PE3 ||
|-
|-
| data-sort-value="E11" | E11 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="B14" | B14 || VD_CECI1 ||
|-
|-
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="A15" | A15 || BE_POW_FAIL || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 7
|-
|-
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#afa}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
| data-sort-value="B15" | B15 || POW_FAIL || Connected to [[Components#Mitsumi_PST3642UL_.28IC_for_CMOS_System_Reset.29|Mitsumi PST3642UL]] (IC6023) pin 4. Used to monitor the state of +12V_MAIN power rail
|-
|-
| data-sort-value="E14" | E14 || {{cellcolors|#afa}} SIF_AD13 || SIF_BC_AD13 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C14
| data-sort-value="F13" | F13 || SW_5_B || rowspan="8" | D || Connected to [[Regulators#Rohm_BD3520FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3520FVM-TR]] (IC6200) pin 3 (switches +1.2V_RSX_VDDR)
|-
|-
| data-sort-value="E99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |
| data-sort-value="F12" | F12 || MK_EN || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 16
|-
|-
| data-sort-value="F01" | F1 || {{cellcolors|#bbf}} PCI_AD20 || BC_PCI_AD20 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU28
| data-sort-value="G13" | G13 || BEVRM_VID5 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 30
|-
|-
| data-sort-value="F02" | F2 || {{cellcolors|#bbf}} PCI_AD22 || BC_PCI_AD22 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW29
| data-sort-value="G12" | G12 || BEVRM_VID4 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 3
|-
|-
| data-sort-value="F03" | F3 || {{cellcolors|#bbf}} PCI_AD18 || BC_PCI_AD18 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU27
| data-sort-value="H13" | H13 || BEVRM_VID3 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 2
|-
|-
| data-sort-value="F04" | F4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="H12" | H12 || BEVRM_VID2 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 1
|-
|-
| data-sort-value="F05" | F5 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="J13" | J13 || BEVRM_VID1 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 32
|-
|-
| data-sort-value="F06" | F6 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="J12" | J12 || BEVRM_VID0 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 31
|-
|-
| data-sort-value="F07" | F7 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K13" | K13 || PC7 || rowspan="8" | C || Not connected in retail PS3 models (testpad CL4085)
|-
|-
| data-sort-value="F08" | F8 || {{cellcolors|#333|#fff}} TEST_IN_2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K12" | K12 || I2CBUS_EN || Connected to [[Components#Toshiba_TC7WB66FK.28TE85R.29_.28low_on-resistance.2C_high-speed_CMOS2-bit_bus_switch.29|Toshiba TC7WB66FK]] pins 3 and 7 (IC5005 on [[SEM-001]]) through 1K resistor (in COK-001 the resistor is missing, a.k.a. this syscon line is N/C). This chip "duplicates" the MK_I2C_SCL/MK_I2C_SDA bus into a secondary XCG_I2C_SCL/XCG_I2C_SDA bus for the clock reference chip/s
|-
|-
| data-sort-value="F09" | F9 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="L13" | L13 || RSXVRM_VID5 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 30
|-
|-
| data-sort-value="F10" | F10 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="L12" | L12 || RSXVRM_VID4 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 3
|-
|-
| data-sort-value="F11" | F11 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="M13" | M13 || RSXVRM_VID3 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 2
|-
|-
| data-sort-value="F12" | F12 || {{cellcolors|#eee|#888}} GPIO15_0 || CL7306 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="M12" | M12 || RSXVRM_VID2 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 1
|-
|-
| data-sort-value="F13" | F13 || {{cellcolors|#afa}} SIF_AD12 || SIF_BC_AD12 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A15
| data-sort-value="N13" | N13 || RSXVRM_VID1 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 32
|-
|-
| data-sort-value="F14" | F14 || {{cellcolors|#afa}} SIF_AD24 || SIF_BC_AD24 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B11
| data-sort-value="N12" | N12 || RSXVRM_VID0 || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 31
|-
|-
| data-sort-value="F99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="T15" | T15 || SW_8_A || rowspan="8" | B || Connected to [[Regulators#Rohm_BD3504FVM-TR_.28Single_channel_Regulator_Driver_IC.29 | Rohm BD3504FVM-TR]] (IC6304) pin 3 (switches +1.5V_YC_RC_VDDA)<br>Connected to [[Regulators#Texas_Instruments_TPS73101DBVRG4_.28Single_Output_LDO.2C_150mA.2C_Adj._1.2-5.5V_SOT23-5.29 | Texas Instruments TPS73101DBVRG4]] (IC6007) pin 3 (switches +1.6V_BE_VDDA)
|-
|-
| data-sort-value="G01" | G1 || {{cellcolors|#bbf}} PCI_AD21 || BC_PCI_AD21 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT28
| data-sort-value="R14" | R14 || SW_7_A || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6103) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6107) pin 1<br>Switches +1.0V_BE_VDDC<br>Cell BE core voltage supply (VDD) then VCS (the core array voltage). Note, the VID values stored on the CELL itself are not available to be read yet. So the default VID of the VRM is used until then.
|-
|-
| data-sort-value="G02" | G2 || {{cellcolors|#bbf}} PCI_AD23 || BC_PCI_AD23 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV29
| data-sort-value="T14" | T14 || SW_6 || Connected to [[Regulators#Rohm_BD3520FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3520FVM-TR]] (IC6303) pin 3 (switches +1.2V_YC_RC_VDDIO)<br>Connected to [[Regulators#Mitsumi_MM3141CNRE_.28150mA_Regulator_Monolithic.29 | Mitsumi MM3141CNRE]] (IC6012) pin 3 (switches +1.2V_MC2_VDDIO)<br>I/O voltage supplies, VDD_IO for [[CELL]], [[RSX]] and [[South Bridge]]
|-
|-
| data-sort-value="G03" | G3 || {{cellcolors|#99f}} PCI_IDSEL || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="R13" | R13 || SW_1_B || Connected to [[Regulators#Mitsumi_MM1562ZFBE_.28Low-Saturation_500mA_Regulators.29 | Mitsumi MM1562ZFBE]] (IC6013) pin 5 (switches +2.5V_LREG_XCG_500_MEM)<br>Connected to [[Components#Toshiba_TC7WB66FK.28TE85R.29_.28low_on-resistance.2C_high-speed_CMOS2-bit_bus_switch.29|Toshiba TC7WB66FK]] (IC5005) pins 3 and 7, and to (IC5006) pin 4, through 1K resistor. The TC7WB66FK chip "duplicates" the MK_I2C_SCL/MK_I2C_SDA bus into a secondary XCG_I2C_SCL/XCG_I2C_SDA bus for the clock reference chip/s<br>Analog Voltage for the core PLL of IC5004, Clock Generator used to support the Rambus XDR memory subsystem and Redwood logic interface.
|-
|-
| data-sort-value="G04" | G4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="T13" | T13 || SW_4_B || Connected to 88E6108 ethernet controller (IC3503) pin 94 (signal named P3_ENABLE_PD)<br>Connected to (Q6003) transistor (switches +3.3V_SB_VDDIO)<br>Connected to [[Regulators#OnSemi_NCP511SN25T1G_.282.5V_150_mA_CMOS_Low_Iq_Low-Dropout_Voltage_Regulator.29 | OnSemi NCP511SN25T1G]] (IC6011) pin 3 (switches +2.5V_SB_PLL_VDDC)<br>Connected to [[Regulators#Mitsumi_MM1591JFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591JFBEG]] (IC6014) pin 5 (switches +1.8V_SB_PERI)<br>Connected to UMH2NTN dual transistor (Q6006) pin 5 (switches +5V_USB)
|-
|-
| data-sort-value="G05" | G5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="R12" | R12 || SW_3 || Connected to [[Regulators#Rohm_BD3520FVM-TR_.28Single_channel_Regulator_Driver_IC.29|Rohm BD3520FVM-TR]] (IC6305) pin 3 (switches +1.2V_SB_VDDC and +1.2V_SB_VDDR)
|-
|-
| data-sort-value="G06" | G6 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="T12" | T12 || VD_CECO1 ||
|-
|-
| data-sort-value="G07" | G7 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="R11" | R11 || VD_CECO0 ||
|-
|-
| data-sort-value="G08" | G8 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="N07" | N7 || STBY_LED || rowspan="8" | A || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 7
|-
|-
| data-sort-value="G09" | G9 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="M07" | M7 || POW_LED || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 6
|-
|-
| data-sort-value="G10" | G10 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="N06" | N6 || AUDIO_MUTE || Connected to transistor DTA144EUA-T106 (Q2404). Switches [[Components#Cirrus_CX4351-CZZR|Cirrus CX4351-CZZR]] pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to [[Connectors#AV_Multi_Out_pinout_-_CN2401_12P|MultiAV connector]] pin 11 (AUL) and pin9 (AUR) respectivelly
|-
|-
| data-sort-value="G11" | G11 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="M06" | M6 || PA4 || Not connected in retail PS3 models (testpad CL4087)
|-
|-
| data-sort-value="G12" | G12 || {{cellcolors|#eee|#888}} GPIO15_1 || CL7311 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="N05" | N5 || BT_RESET || Connected to wifi board connector (CN3701) pin 10 (named SYSCON_RST). This is a syscon output
|-
|-
| data-sort-value="G13" | G13 || {{cellcolors|#afa}} SIF_AD16 || SIF_BC_AD16 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A14
| data-sort-value="M05" | M5 || WLAN_RESET || Connected to wifi board connector (CN3701) pin 29 (named 11G_RESET). This is a syscon output
|-
|-
| data-sort-value="G14" | G14 || {{cellcolors|#afa}} SIF_AD23 || SIF_BC_AD23 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A10
| data-sort-value="N04" | N4 || SW_5_A || Connected to [[Regulators#OnSemi_NCP5318FTR2G_.28Two.2FThree.2FFour-Phase_Buck_CPU_Controller.29|OnSemi NCP5318FTR2G]] (IC6201) pin 29<br>Connected to [[Components#Toshiba_TC7SG08FU_.282_Input_AND_Gate.29|Toshiba TC7SG08FU]] (IC6204) pin 1<br>Switches +1.2V_RSX_VDDC
|-
|-
| data-sort-value="G99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="M04" | M4 || PA0 || Not connected in retail PS3 models (testpad CL4092)
|-
|-
| data-sort-value="H01" | H1 || {{cellcolors|#bbf}} PCI_AD15 || BC_PCI_AD15 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT23
| data-sort-value="J16" | J16 || RBB || rowspan="12" | <abbr title="EEPROM Interface">EEP</abbr> ||
|-
|-
| data-sort-value="H02" | H2 || {{cellcolors|#bbf}} PCI_AD16 || BC_PCI_AD16 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW27
| data-sort-value="K16" | K16 || PI7 ||
|-
|-
| data-sort-value="H03" | H3 || {{cellcolors|#bbf}} PCI_AD19 || BC_PCI_AD19 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT27
| data-sort-value="J15" | J15 || WCB ||
|-
|-
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="K15" | K15 || PI6 ||
|-
|-
| data-sort-value="H05" | H5 || {{cellcolors|#333|#fff}} TEST_PLL_BP_0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E16" | E16 || SKB ||
|-
|-
| data-sort-value="H06" | H6 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E15" | E15 || PP3 ||
|-
|-
| data-sort-value="H07" | H7 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="G16" | G16 || DI ||
|-
|-
| data-sort-value="H08" | H8 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="G15" | G15 || PP2 ||
|-
|-
| data-sort-value="H09" | H9 || {{cellcolors|#f93|#fff}} VDD2 || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="H16" | H16 || DO ||
|-
|-
| data-sort-value="H10" | H10 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="H15" | H15 || PP1 ||
|-
|-
| data-sort-value="H11" | H11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="F16" | F16 || CSB ||
|-
|-
| data-sort-value="H12" | H12 || {{cellcolors|#eee|#888}} GPIO15_2 || CL7305 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F15" | F15 || PP0 ||
|-
|-
| data-sort-value="H13" | H13 || {{cellcolors|#afa}} SIF_AD22 || SIF_BC_AD22 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C13
| data-sort-value="H11" | H11 || TESTMODE || rowspan="9" | <abbr title="Reset & Clock">RST</abbr> ||
|-
|-
| data-sort-value="H14" | H14 || {{cellcolors|#afa}} SIF_AD25 || SIF_BC_AD25 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B10
| data-sort-value="B16" | B16 || OSCOUT || Connected to crystal 32.768Khz
|-
|-
| data-sort-value="H99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="C16" | C16 || OSCIN || Connected to crystal 32.768Khz
|-
|-
| data-sort-value="J01" | J1 || {{cellcolors|#bbf}} PCI_AD14 || BC_PCI_AD14 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU23
| data-sort-value="D16" | D16 || 32KOUT || Connected to resistor 1K to +3.3V_EVER
|-
|-
| data-sort-value="J02" | J2 || {{cellcolors|#bbf}} PCI_AD17 || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="D15" | D15 || 32KIN || Connected to resistor 22ohm to pad D16
|-
|-
| data-sort-value="J03" | J3 || data-sort-value="PCI_AD06" {{cellcolors|#bbf}} PCI_AD6 || data-sort-value="BC_PCI_AD06" | BC_PCI_AD6 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW21
| data-sort-value="T05" | T5 || EXTAL || Connected to crystal 16.9344Mhz
|-
|-
| data-sort-value="J04" | J4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="T04" | T4 || XTAL || Connected to crystal 16.9344Mhz
|-
|-
| data-sort-value="J05" | J5 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="T07" | T7 || XXTALO || Not connected (testpad CL4040)
|-
|-
| data-sort-value="J06" | J6 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="J11" | J11 || RST || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 8
|-
|-
| data-sort-value="J07" | J7 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="R04" | R4 || AVSUO || rowspan="35" | <abbr title="Power port>PWR</abbr> || Ground
|-
|-
| data-sort-value="J08" | J8 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="R05" | R5 || AVDUO || +3.3V_EVER
|-
|-
| data-sort-value="J09" | J9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="G06" | G6 || AVSS || Ground
|-
|-
| data-sort-value="J10" | J10 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C02" | C2 || AVREF2 || Ground
|-
|-
| data-sort-value="J11" | J11 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="B01" | B1 || AVREF1 || +3.3V_EVER
|-
|-
| data-sort-value="J12" | J12 || {{cellcolors|#eee|#888}} GPIO33_0 || CL7310 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F07" | F7 || AVDD || +3.3V_EVER
|-
|-
| data-sort-value="J13" | J13 || {{cellcolors|#afa}} SIF_AD19 || SIF_BC_AD19 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B13
| data-sort-value="K11" | K11 || VSSF || Ground
|-
|-
| data-sort-value="J14" | J14 || {{cellcolors|#afa}} SIF_AD27 || SIF_BC_AD27 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C10
| data-sort-value="K06" | K6 || VSSF || Ground
|-
|-
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="L06" | L6 || VDDF || +3.3V_EVER
|-
|-
| data-sort-value="K01" | K1 || data-sort-value="PCI_AD09" {{cellcolors|#bbf}} PCI_AD9 || data-sort-value="BC_PCI_AD09" | BC_PCI_AD9 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT21
| data-sort-value="G06" | G7 || rowspan="8" | VSS || rowspan="8" | Ground
|-
|-
| data-sort-value="K02" | K2 || {{cellcolors|#bbf}} PCI_AD11 || BC_PCI_AD11 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT22
| data-sort-value="G08" | G8
|-
|-
| data-sort-value="K03" | K3 || {{cellcolors|#bbf}} PCI_AD10 || BC_PCI_AD10 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU22
| data-sort-value="G10" | G10
|-
|-
| data-sort-value="K04" | K4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="T06" | T6
|-
|-
| data-sort-value="K05" | K5 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="R06" | R6
|-
|-
| data-sort-value="K06" | K6 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="T03" | T3
|-
|-
| data-sort-value="K07" | K7 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="L01" | L1
|-
|-
| data-sort-value="K08" | K8 || {{cellcolors|#333|#fff}} TEST_PLL_BP_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E01" | E1
|-
|-
| data-sort-value="K09" | K9 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C15" | C15 || VSSep || EEPROM Ground
|-
|-
| data-sort-value="K10" | K10 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="G11" | G11 || VDDep || EEPROM Power (+3.3V_EVER)
|-
|-
| data-sort-value="K11" | K11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F11" | F11 || VDDbat || +battery
|-
|-
| data-sort-value="K12" | K12 || {{cellcolors|#eee|#888}} GPIO33_1 || CL7304 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="H07" | H7 || rowspan="7" | DVDD || rowspan="7" | +1.8V_EVER
|-
|-
| data-sort-value="K13" | K13 || {{cellcolors|#afa}} SIF_AD17 || SIF_BC_AD17 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A13
| data-sort-value="J10" | J10
|-
|-
| data-sort-value="K14" | K14 || {{cellcolors|#8f8}} SIF_BREQ || BREQ_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A7
| data-sort-value="K10" | K10
|-
|-
| data-sort-value="K99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="L10" | L10
|-
|-
| data-sort-value="L01" | L1 || data-sort-value="PCI_AD03" {{cellcolors|#bbf}} PCI_AD3 || data-sort-value="BC_PCI_AD03" | BC_PCI_AD3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT19
| data-sort-value="L11" | L11
|-
|-
| data-sort-value="L02" | L2 || data-sort-value="PCI_AD07" {{cellcolors|#bbf}} PCI_AD7 || data-sort-value="BC_PCI_AD07" | BC_PCI_AD7 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV21
| data-sort-value="R07" | R7
|-
|-
| data-sort-value="L03" | L3 || {{cellcolors|#bbf}} PCI_AD13 || BC_PCI_AD13 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV23
| data-sort-value="J07" | J7
|-
|-
| data-sort-value="L04" | L4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="F08" | F8 || rowspan="5" | VDD3 || rowspan="5" | +3.3V_EVER
|-
|-
| data-sort-value="L05" | L5 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F10" | F10
|-
|-
| data-sort-value="L06" | L6 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="H10" | H10
|-
|-
| data-sort-value="L07" | L7 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="J06" | J6
|-
|-
| data-sort-value="L08" | L8 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="F06" | F6
|-
|-
| data-sort-value="L09" | L9 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="D02" | D2 || VDD2 || +1.5V_RSX_VDDIO
|-
|-
| data-sort-value="L10" | L10 || {{cellcolors|#c33|#fff}} VDDS || +3.3V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1593DFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1593DFBEG]] (IC6022) pin 1
| data-sort-value="R03" | R3 || VDD1 || +1.2V_MC2_VDDIO
|-
|-
| data-sort-value="L11" | L11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="L02" | L2 || VDD0 || +1.2V_MC2_VDDIO
|-
|-
| data-sort-value="L12" | L12 || {{cellcolors|#eee|#888}} GPIO33_2 || CL7309 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="A16" | A16 || rowspan="6" colspan="3"| NC
|-
|-
| data-sort-value="L13" | L13 || {{cellcolors|#8f8}} SIF_BGNT || BGNT_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B7
| data-sort-value="T16" | T16
|-
|-
| data-sort-value="L14" | L14 || {{cellcolors|#8f8}} SIF_GINT || SGINT_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B6
| data-sort-value="T01" | T1
|-
|-
| data-sort-value="L99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="A01" | A1
|-
|-
| data-sort-value="M01" | M1 || data-sort-value="PCI_AD04" {{cellcolors|#bbf}} PCI_AD4 || data-sort-value="BC_PCI_AD04" | BC_PCI_AD4 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU20
| data-sort-value="G09" | G9
|-
|-
| data-sort-value="M02" | M2 || data-sort-value="PCI_AD02" {{cellcolors|#bbf}} PCI_AD2 || data-sort-value="BC_PCI_AD02" | BC_PCI_AD2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU19
| data-sort-value="F09" | F9
|-
|-
| data-sort-value="M03" | M3 || data-sort-value="PCI_AD01" {{cellcolors|#bbf}} PCI_AD1 || data-sort-value="BC_PCI_AD01" | BC_PCI_AD1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV19
| data-sort-value="L08" | L8 || JRTCK || rowspan="6" | JTAG || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 4
|-
|-
| data-sort-value="M04" | M4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K08" | K8 || JTCK || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 5
|-
|-
| data-sort-value="M05" | M5 || {{cellcolors|#99f}} PCI_STOP || BC_PCI_STOP || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV25
| data-sort-value="K09" | K9 || JTDO || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 6
|-
|-
| data-sort-value="M06" | M6 || {{cellcolors|#99f}} PCI_PAR || BC_PCI_PAR || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU24
| data-sort-value="L09" | L9 || JTMS || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 7
|-
|-
| data-sort-value="M07" | M7 || {{cellcolors|#99f}} PCI_TRDY || BC_PCI_TRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT25
| data-sort-value="K07" | K7 || JTDI || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 3
|-
|-
| data-sort-value="M08" | M8 || {{cellcolors|#77f}} PCI_CBE0 || BC_PCI_CBE0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP19
| data-sort-value="L07" | L7 || JNTRST || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 2 ?
|-
|-
| data-sort-value="M09" | M9 || {{cellcolors|#99f}} PCI_FRAME || BC_PCI_FRAME || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT26
| data-sort-value="A06" | A6 || MC_RESERVED2 || rowspan="4" | R || Not connected to BluRay Drive because a missing resistor (R4080). BD_LED
|-
|-
| data-sort-value="M10" | M10 || {{cellcolors|#99f}} PCI_RST || BC_PCI_RST || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP29 through a 22 ohm resistor
| data-sort-value="B06" | B6 || MC_P_OFF_REQ || Connected to BluRay Drive connector (CN3221) pin 48
|-
|-
| data-sort-value="M11" | M11 || {{cellcolors|#ff4|#f00}} SW1.5 || SW1.5 || {{pino}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 5 (switches +1.5V_EEGS_VDDO)
| data-sort-value="A07" | A7 || MC_ALIVE || Connected to BluRay Drive connector (CN3221) pin 47
|-
|-
| data-sort-value="M12" | M12 || {{cellcolors|#eee|#888}} GPIO33_3 || CL7303 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="B07" | B7 || MC_RESERVED1 || Connected to BluRay Drive connector (CN3221) pin 49
|-
|-
| data-sort-value="M13" | M13 || {{cellcolors|#4c4}} VBLK || EEGS_VBLK1 || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A4 ('''V'''ertical '''BL'''an'''K''')
| data-sort-value="R10" | R10 || RMC_IN || rowspan="7" | Q || Connected to [[Switch_boards|Switch board]] [[CSW-001]] connector pin 3<br> Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 17
|-
|-
| data-sort-value="M14" | M14 || {{cellcolors|#4c4}} HBLK || EEGS_HBLK1 || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B5 ('''H'''orizontal '''BL'''an'''K''')
| data-sort-value="T11" | T11 || PQ5 ||
|-
|-
| data-sort-value="M99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="T10" | T10 || PQ4 ||
|-
|-
| data-sort-value="N01" | N1 || data-sort-value="PCI_AD08" {{cellcolors|#bbf}} PCI_AD8 || data-sort-value="BC_PCI_AD08" | BC_PCI_AD8 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU21
| data-sort-value="T08" | T8 || THR_I2C_SCL ||
|-
|-
| data-sort-value="N02" | N2 || data-sort-value="PCI_AD05" {{cellcolors|#bbf}} PCI_AD5 || data-sort-value="BC_PCI_AD05" | BC_PCI_AD5 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT20
| data-sort-value="T09" | T9 || THR_I2C_SDA ||
|-
|-
| data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="R09" | R9 || PQ1 ||
|-
|-
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#bbf}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
| data-sort-value="R08" | R8 || RSX_FBVDD_SEL || Connected to [[Components#Texas_Instruments_SN105233DBTR|Texas Instruments SN105233DBTR]] (IC6301) through transistor/s
|-
|-
| data-sort-value="N05" | N5 || {{cellcolors|#99f|#a00}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24 (system error)
| data-sort-value="P16" | P16 || UART0_TxD || rowspan="4" | P || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 11 (Serial Transmit)
|-
|-
| data-sort-value="N06" | N6 || {{cellcolors|#99f}} PCI_DEVSEL || BC_PCI_DEVSEL || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU25
| data-sort-value="P15" | P15 || UART0_RxD || Connected to [[Service_Connectors#CN4009| service connector]] (CN4009) pin 10 (Serial Receive)
|-
|-
| data-sort-value="N07" | N7 || {{cellcolors|#77f}} PCI_CBE2 || BC_PCI_CBE2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AP20
| data-sort-value="R16" | R16 || HDMI_I2C_SCL || Connected to [[Sil9132CBU|HDMI controller Sil9132CBU]] pad E2
|-
|-
| data-sort-value="N08" | N8 || {{cellcolors|#99f}} PCI_GNT || BC_PCI_GNT1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN24
| data-sort-value="R15" | R15 || HDMI_I2C_SDA || Connected to [[Sil9132CBU|HDMI controller Sil9132CBU]] pad D2
|-
|-
| data-sort-value="N09" | N9 || {{cellcolors|#ff4|#f00}} SW2.65 || SW2.65 || {{pino}} || Connected to [[Regulators#Mitsumi_MM1662YHBE_.281000_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1662YHBE]] (IC6607) pin 5 (switches +2.5V_RDRAM_VDD)
| data-sort-value="D01" | D1 || MK_I2C_SCL || rowspan="10" | O || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 46
|-
|-
| data-sort-value="N10" | N10 || {{cellcolors|#ff4|#f00}} SW3.3 || SW3.3 || {{pino}} || Connected to [[Regulators#Mitsumi_MM1573ENRE_.28150_mA_CMOS_Low_noise_Voltage_Regulator.29 | Mitsumi MM1573ENRE]] (IC6605) pin 3 (switches +3.3V_DRCG_VDD)
| data-sort-value="C01" | C1 || MK_I2C_SDA || Connected to [[Timebases#ICS_ICS1493G-18LFT|ICS1493G-18LFT]] clock generator (IC5001) pin 47
|-
|-
| data-sort-value="N11" | N11 || {{cellcolors|#ff4|#f00}} SW1.81 || SW1.81 || {{pino}} || Connected to [[Regulators#Mitsumi_MM1561JFBE_.28Low-Saturation_500mA_Regulators.29 | Mitsumi MM1561JFBE]] (IC6603) pin 5 (switches +1.8V_EEGS_VDDIO)
| data-sort-value="G04" | G4 || HDMI_RST1 || Not connected ? (it seems to be a secondary reset signal for [[Sil9132CBU|HDMI controller Sil9132CBU]] never used in retail PS3 models)
|-
|-
| data-sort-value="N12" | N12 || {{cellcolors|#eee|#888}} GPIO33_4 || CL7308 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F04" | F4 || HDMI_RST0 || Connected to [[Sil9132CBU|HDMI controller Sil9132CBU]] pad G2 ?
|-
|-
| data-sort-value="N13" | N13 || {{cellcolors|#ff8}} PCLKEN || PCLKEN || {{pino}} || Connected to base pin of DTC144EUA-T106 transistor (Q2101) to switch [[TC7WP3125FK]] (IC2105) and generate the clock DRCG_GEN18M<br>DRCG_GEN18M is a input of the [[Components#ICS_ICS626BGLFT|Renesas ICS626BGLFT]] (IC7001) that generates the clocks for the communications in between EEGS and the RDRAM chips (CTMA/CTMNA and CTMB/CTMNB)
| data-sort-value="G05" | G5 || SW_AVCG<br>PO5 || Connected to [[Timebases#ICS_ICS422AG-07LFT_.28IC_CLOCK_GEN_RSX_AV_CLK_24-TSSOP.29|ICS422AG-07LFT]] (IC2102) pin 12 (switches RSX_AVCLK0, RSX_AVCLK1, RSX_AVCLK2, RSX_AVCLK3) clocks for [[RSX]] and indirectly for EEGS<->RDRAM
|-
|-
| data-sort-value="N14" | N14 || {{cellcolors|#dd4|#080}} EGRST || EGRST || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B4 (control line to reset EEGS)
| data-sort-value="F05" | F5 || DISC_IN_MECHA || Connected to BluRay Drive connector (CN3221) pin 55
|-
|-
| data-sort-value="N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="E04" | E4 || EJECT_MECHA || Connected to BluRay Drive connector (CN3221) pin 56
|-
|-
| data-sort-value="P01" | P1 || {{cellcolors|#bbf}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
| data-sort-value="D04" | D4 || XDR_FET_RST || XDR_RQ_RST
|-
|-
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E05" | E5 || PO0 || Not connected (testpad CL4086)
|-
|-
| data-sort-value="P03" | P3 || {{cellcolors|#99f}} PCI_CLK || BC_PCI_CLK || {{pini}} || Connected to [[Timebases#ICS_ICS1493G-18LFT | ICS1493G-18LFT]] (IC5001) pin 5<br>Connected to [[South Bridge]] [[CXD2973GB]] pad AP28 through a 49.9 ohm resistor
| data-sort-value="D05" | D5 || XCG_EN || Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)<br>Connected to [[Timebases#ICS_ICS9218AGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9218AGLFT]] (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)<br>Connected to [[Timebases#ICS_ICS9214DGLFT_.28IC_CLOCK_GEN_RAMBUS_XDR_28-TSSOP.29|ICS9214DGLFT]] (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N)
|-
|-
| data-sort-value="P04" | P4 || {{cellcolors|#77f}} PCI_CBE1 || BC_PCI_CBE1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN19
| data-sort-value="K02" | K2 || VD_VINT1 || rowspan="11" | N ||
|-
|-
| data-sort-value="P05" | P5 || {{cellcolors|#99f|#a00}} PCI_PERR || BC_PCI_PERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW25 (parity error)
| data-sort-value="K01" | K1 || VD_VINT0 ||
|-
|-
| data-sort-value="P06" | P6 || {{cellcolors|#99f}} PCI_IRDY || BC_PCI_IRDY || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU26
| data-sort-value="J02" | J2 || RSX_INT ||
|-
|-
| data-sort-value="P07" | P7 || {{cellcolors|#77f}} PCI_CBE3 || BC_PCI_CBE3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN20
| data-sort-value="J01" | J1 || RSX_FLDO1 ||
|-
|-
| data-sort-value="P08" | P8 || {{cellcolors|#99f}} PCI_REQ || BC_PCI_REQ1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AN22
| data-sort-value="H02" | H2 || PN6 ||
|-
|-
| data-sort-value="P09" | P9 || {{cellcolors|#ff4|#f00}} SW1.8 || SW1.8 || {{pino}} || Connected to a missing component (IC6604) pin 3 (switches +1.8V_RDRAM_VCMOS)
| data-sort-value="H01" | H1 || PN5 ||
|-
|-
| data-sort-value="P10" | P10 || {{cellcolors|#ff4|#f00}} SW2.5 || SW2.5 || {{pino}} || Connected to [[Regulators#OnSemi_NCP511SN25T1G_.282.5V_150_mA_CMOS_Low_Iq_Low-Dropout_Voltage_Regulator.29 | OnSemi NCP511SN25T1G]] (IC6601) pin 3 (switches +2.5V_EEGS_PLLVDD1)
| data-sort-value="G02" | G2 || RSX_RESET ||
|-
|-
| data-sort-value="P11" | P11 || {{cellcolors|#ff4|#f00}} SW1.2 || SW1.2 || {{pino}} || Connected to [[Regulators#Rohm_BD3504FVM-TR_.28Single_channel_Regulator_Driver_IC.29 | Rohm BD3504FVM-TR]] (IC6602) pin 3 (switches +1.2V_EEGS_VDD)
| data-sort-value="G01" | G1 || RSX_SPI_CLK || rowspan="4" | RSX SPI Bus
|-
|-
| data-sort-value="P12" | P12 || {{cellcolors|#ff4|#f00}} SW3.1 || SW3.1 || {{pino}} || Connected to [[Regulators#Mitsumi_MM3143BNRE_.28150_mA_CMOS_Low_noise_Voltage_Regulator.29 | Mitsumi MM3143BNRE]] (IC6600) pin 3 (switches +3.1V_EEGS_AVDA)
| data-sort-value="F02" | F2 || RSX_SPI_DO
|-
|-
| data-sort-value="P13" | P13 || {{cellcolors|#eee|#888}} GPIO33_7 || CL7301 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F01" | F1 || RSX_SPI_DI
|-
|-
| data-sort-value="P14" | P14 || {{cellcolors|#dd4|#080}} PWRUP_EE || PWRUP_EE || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad Y1 (control line to power EEGS)
| data-sort-value="E02" | E2 || RSX_SPI_CS
|}
|}</div><noinclude>[[Category:Templates]]</noinclude>
 
{{Motherboard Components}}<noinclude>[[Category:Main]]</noinclude>

Revision as of 12:01, 20 October 2022

Sony CXD9208GP (PS2 bridge chip)

PS2 bridge chip, from EE+GS to South Bridge

6-710-433-01 / IC7301

Used on PS3 FAT CECHAxx/COK-001 and CECHBxx/COK-001
PS2 bridge located in between EE+GS and the South Bridge

Mullion syscons, bottom view
With pad A1 mark at south-east corner

Mullion syscon, top view
With pad A1 mark at south-west corner
[ View ], [ Discuss ] or [ Edit ]
Syscon pinout BGA 200 pads
Pad Name Port Description
T2 BE_INT M Connected to CELL 90nm pad AW19
R1 PM7
R2 PM6
P1 BE_POWGOOD Connected to CELL 90nm pad AV20
P2 BE_RESET Connected to CELL 90nm pad AW20
N1 BE_SPI_CLK Connected to CELL 90nm pad AY13 (SPI Bus)
N2 BE_SPI_DO Connected to CELL 90nm pad AV13 (SPI Bus)
M1 BE_SPI_DI Connected to CELL 90nm pad AR13 (SPI Bus)
M2 BE_SPI_CS Connected to CELL 90nm pad AP13 (SPI Bus)
L4 PL8 L unused
L5 PL7
K4 PL6
K5 PL5
J4 PL4
J5 PL3
H4 PL2
H5 PL1
H6 PL0
A8 SB_SPI_CLK K Southbridge SPI Bus
B8 SB_SPI_DO
A9 SB_SPI_DI
B9 SB_SPI_CS
A10 DVE_I2C_SCL Connected to Digital Video Encoder CXM4024R pin 35
B10 DVE_I2C_SDA Connected to Digital Video Encoder CXM4024R pin 36
A11 ACDC_STBY Connected to Power Supply (small connector). This signal enables +12V_MAIN power rail (big prongs)
B11 PK0
B5 DVE_RST J Connected to Digital Video Encoder CXM4024R pin 31 ?
A5 DISC_OUT12_SW Connected to BluRay Drive connector (CN3221) pin 58
B2 DISC_OUT8_SW Connected to BluRay Drive connector (CN3221) pin 57
A2 DISC_IN Connected to BluRay Drive connector (CN3221) pin 52
B3 PJ3 Not connected in retail PS3 models (testpad CL4089)
A3 SW_0 Connected to Fujitsu MB39A116PFT (IC6003) pin 9 (switches +5V_MISC)
Connected to Fujitsu MB39A116PFT (IC6003) pin 10 (switches +3.3V_MISC)
Connected to Texas Instruments SN105233DBTR (IC6301) pin 10 (switches +1.7_MISC)
B4 SW_8_B Connected to Mitsumi MM1561JFBE (IC2408) pin 5 (switches +1.8V_ANA)
Connected to Mitsumi MM1593DFBEG (IC2407) pin 5 (switches +3.3V_ANA)
Connected to transistor DTC144EUA-T106 (Q2401) base pin (switches +5V_ANA ?)
Connected to OnSemi NCP511SN15T1G (IC6019) pin 3 (switches +1.5V_AVCG_VDDIO)
Connected to Rohm BD3521FVM-TR (IC6017) pin 3 (switches +1.5V_RSX_VDDIO)
A4 SW_8_C Connected to Texas Instruments SN105233DBTR (IC6301) pin 9 (switches +1.8V_RSX_FBVDDQ)
Connected to OnSemi NCP511SN18T1 (IC6008) pin 3 (switches +1.8V_RSX_PLL_VDD)
L16 SW_PCI I Connected to Mitsumi MM1591FFBEG (IC6021) pin 5 (switches +1.5V_BRIDGE) for the PS2 bridge CXD9208GP
Connected to Mitsumi MM1593DFBEG (IC6022) pin 5 (switches +3.3V_BRIDGE) for the PS2 bridge CXD9208GP
Connected to PCI service connector pin 80
L15 DISC_CHUCK Connected to BluRay Drive connector (CN3221) pin 54
M16 DISC_PHOT_LED Connected to BluRay Drive connector (CN3221) pin 53
M15 SW_2 Connected to Texas Instruments TPS51117PWRG4 (IC6302) pin 1 (switches +1.8V_VDD_MEM)
N16 DIAG_MODE Connected to service connector (CN4009) pin 13
N15 BACKUP_MODE Connected to service connector (CN4009) pin 14
E6 HDMI_INT H Connected to TC7WP3125FK (IC2501) pin 6. This is a syscon input at 3.3V
The TC7WP3125FK converts the signal originally triggered by Sil9132CBU pad E10 ? at 1.5V and converts it to 3.3V for syscon
The TC7WP3125FK also converts the signal RS_SPDO0 (at 1.5V) into RS_SPDO0_33 (at 3.3V)
D6 VD_CECI0
E7 MECHA_INT Not connected in retail PS3 models (testpad CL4102). The related SouthBridge pad is tied to GND with a 10k resistor (R3163)
D7 RSX_POW_FAIL Connected to OnSemi NCP5318FTR2G (IC6201) pin 7
E8 MUL_CHKSTP_IN SB_CHKSTP_OUT
D8 MUL_TRG_IN Connected to missing components (IC4003, IC4004, IC4005) pin 3 and 6 (related with BE_TRG_IN/OUT, RSX_TRG_IN/OUT, SB_TRG_IN/OUT)
E9 SYS_THR_ALRT Connected to CELL 90nm pad AP23
D9 SB_INT
M11 SW_ATA G Connected to UMH2NTN dual transistor (Q6009) pin 2 (switches +12V_BD)
Connected to UMH2NTN dual transistor (Q6009) pin 5 (switches +5V_BD)
Connected to UMH2NTN dual transistor (Q6006) pin 2 (switches +5V_HDD)
N11 SW_4_A Connected to wifi board connector (CN3701) pin 9 (named 11G_PWR_EN). This is a syscon output
Connected to base pin of transistor UMH2NTN (Q3501) who switches IC3502 pin 5, and IC3501 pin 3 (+1.2V_ESW, +1.9V_ESW, +3.3V_ESW for Ethernet Controller)
M10 XDR_FET_VREF Connected to transistor DTC144EUA-T106 (Q4008). Switches XDR_RQ_VREF_FET
N10 XDR_FET_SCK BE_RQ_SCK_BJT
M9 BUZZER
N9 SW_PWM Connected to Switch board CSW-001 connector pin 2
M8 FANPWM1 Secondary fan output (non-retail PS3 models only)
N8 FANPWM0 Primary fan output (all PS3 models)
E10 MUL_CHKSTP_OUT F
D10 MUL_TRG_OUT Connected to missing components (IC4006) pin 2 (related with BE_TRG_IN/OUT, RSX_TRG_IN/OUT, SB_TRG_IN/OUT)
E11 SB_CGRESET SB_CGRST (the name indicates that it resets the clock generator for the southbridge)
D11 SB_RESET Connected to 88SA8040-TBC1 SATA2PATA BluRay controller pin 17
Connected to GL852 (IC3305) USB HUB pin 38
Connected to Multi-card-board connector CN3219 pin 7
E12 BT_WAKEON Connected to wifi board connector (CN3701) pin 30 (named BT_WAKE). This is a syscon input
D12 PF2
BE_VCS_1.25_ON
COK-001/COK-002 PF2 (Not connected)
SEM-001 BE_VCS_1.25_ON
E13 PF1
BE_VCS_1.30_ON
COK-001/COK-002 PF1 (Not connected)
SEM-001 BE_VCS_1.30_ON
D13 SW_1_A Connected to Mitsumi MM1593DFBEG (IC6020) pin 5 (switches +3.3V_MK_VDD) for Clock Synthesizer
A12 EJECT_SW E Connected to Switch board CSW-001 connector pin 5
B12 POW_SW Connected to Switch board CSW-001 connector pin 4
A13 SB_EBUS_RESET SS2_RESET (StarShip2 related), not connected because a missing resistor (R4135) ?
B13 SB_EBUS_BRDY SS2_BRDY (StarShip2 related)
A14 PE3
B14 VD_CECI1
A15 BE_POW_FAIL Connected to OnSemi NCP5318FTR2G (IC6103) pin 7
B15 POW_FAIL Connected to Mitsumi PST3642UL (IC6023) pin 4. Used to monitor the state of +12V_MAIN power rail
F13 SW_5_B D Connected to Rohm BD3520FVM-TR (IC6200) pin 3 (switches +1.2V_RSX_VDDR)
F12 MK_EN Connected to ICS1493G-18LFT clock generator (IC5001) pin 16
G13 BEVRM_VID5 Connected to OnSemi NCP5318FTR2G (IC6103) pin 30
G12 BEVRM_VID4 Connected to OnSemi NCP5318FTR2G (IC6103) pin 3
H13 BEVRM_VID3 Connected to OnSemi NCP5318FTR2G (IC6103) pin 2
H12 BEVRM_VID2 Connected to OnSemi NCP5318FTR2G (IC6103) pin 1
J13 BEVRM_VID1 Connected to OnSemi NCP5318FTR2G (IC6103) pin 32
J12 BEVRM_VID0 Connected to OnSemi NCP5318FTR2G (IC6103) pin 31
K13 PC7 C Not connected in retail PS3 models (testpad CL4085)
K12 I2CBUS_EN Connected to Toshiba TC7WB66FK pins 3 and 7 (IC5005 on SEM-001) through 1K resistor (in COK-001 the resistor is missing, a.k.a. this syscon line is N/C). This chip "duplicates" the MK_I2C_SCL/MK_I2C_SDA bus into a secondary XCG_I2C_SCL/XCG_I2C_SDA bus for the clock reference chip/s
L13 RSXVRM_VID5 Connected to OnSemi NCP5318FTR2G (IC6201) pin 30
L12 RSXVRM_VID4 Connected to OnSemi NCP5318FTR2G (IC6201) pin 3
M13 RSXVRM_VID3 Connected to OnSemi NCP5318FTR2G (IC6201) pin 2
M12 RSXVRM_VID2 Connected to OnSemi NCP5318FTR2G (IC6201) pin 1
N13 RSXVRM_VID1 Connected to OnSemi NCP5318FTR2G (IC6201) pin 32
N12 RSXVRM_VID0 Connected to OnSemi NCP5318FTR2G (IC6201) pin 31
T15 SW_8_A B Connected to Rohm BD3504FVM-TR (IC6304) pin 3 (switches +1.5V_YC_RC_VDDA)
Connected to Texas Instruments TPS73101DBVRG4 (IC6007) pin 3 (switches +1.6V_BE_VDDA)
R14 SW_7_A Connected to OnSemi NCP5318FTR2G (IC6103) pin 29
Connected to Toshiba TC7SG08FU (IC6107) pin 1
Switches +1.0V_BE_VDDC
Cell BE core voltage supply (VDD) then VCS (the core array voltage). Note, the VID values stored on the CELL itself are not available to be read yet. So the default VID of the VRM is used until then.
T14 SW_6 Connected to Rohm BD3520FVM-TR (IC6303) pin 3 (switches +1.2V_YC_RC_VDDIO)
Connected to Mitsumi MM3141CNRE (IC6012) pin 3 (switches +1.2V_MC2_VDDIO)
I/O voltage supplies, VDD_IO for CELL, RSX and South Bridge
R13 SW_1_B Connected to Mitsumi MM1562ZFBE (IC6013) pin 5 (switches +2.5V_LREG_XCG_500_MEM)
Connected to Toshiba TC7WB66FK (IC5005) pins 3 and 7, and to (IC5006) pin 4, through 1K resistor. The TC7WB66FK chip "duplicates" the MK_I2C_SCL/MK_I2C_SDA bus into a secondary XCG_I2C_SCL/XCG_I2C_SDA bus for the clock reference chip/s
Analog Voltage for the core PLL of IC5004, Clock Generator used to support the Rambus XDR memory subsystem and Redwood logic interface.
T13 SW_4_B Connected to 88E6108 ethernet controller (IC3503) pin 94 (signal named P3_ENABLE_PD)
Connected to (Q6003) transistor (switches +3.3V_SB_VDDIO)
Connected to OnSemi NCP511SN25T1G (IC6011) pin 3 (switches +2.5V_SB_PLL_VDDC)
Connected to Mitsumi MM1591JFBEG (IC6014) pin 5 (switches +1.8V_SB_PERI)
Connected to UMH2NTN dual transistor (Q6006) pin 5 (switches +5V_USB)
R12 SW_3 Connected to Rohm BD3520FVM-TR (IC6305) pin 3 (switches +1.2V_SB_VDDC and +1.2V_SB_VDDR)
T12 VD_CECO1
R11 VD_CECO0
N7 STBY_LED A Connected to Switch board CSW-001 connector pin 7
M7 POW_LED Connected to Switch board CSW-001 connector pin 6
N6 AUDIO_MUTE Connected to transistor DTA144EUA-T106 (Q2404). Switches Cirrus CX4351-CZZR pin 18 (AOUTA) left audio channel and pin 15 (AOUTB) right audio channel, that are connected to MultiAV connector pin 11 (AUL) and pin9 (AUR) respectivelly
M6 PA4 Not connected in retail PS3 models (testpad CL4087)
N5 BT_RESET Connected to wifi board connector (CN3701) pin 10 (named SYSCON_RST). This is a syscon output
M5 WLAN_RESET Connected to wifi board connector (CN3701) pin 29 (named 11G_RESET). This is a syscon output
N4 SW_5_A Connected to OnSemi NCP5318FTR2G (IC6201) pin 29
Connected to Toshiba TC7SG08FU (IC6204) pin 1
Switches +1.2V_RSX_VDDC
M4 PA0 Not connected in retail PS3 models (testpad CL4092)
J16 RBB EEP
K16 PI7
J15 WCB
K15 PI6
E16 SKB
E15 PP3
G16 DI
G15 PP2
H16 DO
H15 PP1
F16 CSB
F15 PP0
H11 TESTMODE RST
B16 OSCOUT Connected to crystal 32.768Khz
C16 OSCIN Connected to crystal 32.768Khz
D16 32KOUT Connected to resistor 1K to +3.3V_EVER
D15 32KIN Connected to resistor 22ohm to pad D16
T5 EXTAL Connected to crystal 16.9344Mhz
T4 XTAL Connected to crystal 16.9344Mhz
T7 XXTALO Not connected (testpad CL4040)
J11 RST Connected to service connector (CN4009) pin 8
R4 AVSUO PWR Ground
R5 AVDUO +3.3V_EVER
G6 AVSS Ground
C2 AVREF2 Ground
B1 AVREF1 +3.3V_EVER
F7 AVDD +3.3V_EVER
K11 VSSF Ground
K6 VSSF Ground
L6 VDDF +3.3V_EVER
G7 VSS Ground
G8
G10
T6
R6
T3
L1
E1
C15 VSSep EEPROM Ground
G11 VDDep EEPROM Power (+3.3V_EVER)
F11 VDDbat +battery
H7 DVDD +1.8V_EVER
J10
K10
L10
L11
R7
J7
F8 VDD3 +3.3V_EVER
F10
H10
J6
F6
D2 VDD2 +1.5V_RSX_VDDIO
R3 VDD1 +1.2V_MC2_VDDIO
L2 VDD0 +1.2V_MC2_VDDIO
A16 NC
T16
T1
A1
G9
F9
L8 JRTCK JTAG Connected to service connector (CN4009) pin 4
K8 JTCK Connected to service connector (CN4009) pin 5
K9 JTDO Connected to service connector (CN4009) pin 6
L9 JTMS Connected to service connector (CN4009) pin 7
K7 JTDI Connected to service connector (CN4009) pin 3
L7 JNTRST Connected to service connector (CN4009) pin 2 ?
A6 MC_RESERVED2 R Not connected to BluRay Drive because a missing resistor (R4080). BD_LED
B6 MC_P_OFF_REQ Connected to BluRay Drive connector (CN3221) pin 48
A7 MC_ALIVE Connected to BluRay Drive connector (CN3221) pin 47
B7 MC_RESERVED1 Connected to BluRay Drive connector (CN3221) pin 49
R10 RMC_IN Q Connected to Switch board CSW-001 connector pin 3
Connected to service connector (CN4009) pin 17
T11 PQ5
T10 PQ4
T8 THR_I2C_SCL
T9 THR_I2C_SDA
R9 PQ1
R8 RSX_FBVDD_SEL Connected to Texas Instruments SN105233DBTR (IC6301) through transistor/s
P16 UART0_TxD P Connected to service connector (CN4009) pin 11 (Serial Transmit)
P15 UART0_RxD Connected to service connector (CN4009) pin 10 (Serial Receive)
R16 HDMI_I2C_SCL Connected to HDMI controller Sil9132CBU pad E2
R15 HDMI_I2C_SDA Connected to HDMI controller Sil9132CBU pad D2
D1 MK_I2C_SCL O Connected to ICS1493G-18LFT clock generator (IC5001) pin 46
C1 MK_I2C_SDA Connected to ICS1493G-18LFT clock generator (IC5001) pin 47
G4 HDMI_RST1 Not connected ? (it seems to be a secondary reset signal for HDMI controller Sil9132CBU never used in retail PS3 models)
F4 HDMI_RST0 Connected to HDMI controller Sil9132CBU pad G2 ?
G5 SW_AVCG
PO5
Connected to ICS422AG-07LFT (IC2102) pin 12 (switches RSX_AVCLK0, RSX_AVCLK1, RSX_AVCLK2, RSX_AVCLK3) clocks for RSX and indirectly for EEGS<->RDRAM
F5 DISC_IN_MECHA Connected to BluRay Drive connector (CN3221) pin 55
E4 EJECT_MECHA Connected to BluRay Drive connector (CN3221) pin 56
D4 XDR_FET_RST XDR_RQ_RST
E5 PO0 Not connected (testpad CL4086)
D5 XCG_EN Connected to ICS9218AGLFT (IC5002) pin 11 (switches BE_Y0_RQ_CTM/N, BE_Y1_RQ_CTM/N)
Connected to ICS9218AGLFT (IC5003) pin 11 (switches BE_PLL_REFCLK_P/N)
Connected to ICS9214DGLFT (IC5004) pin 11 (switches BE_RC_REFCLK_P/N, RSX_RC_REFCLK_P/N, SB_RC_REFCLK_P/N)
K2 VD_VINT1 N
K1 VD_VINT0
J2 RSX_INT
J1 RSX_FLDO1
H2 PN6
H1 PN5
G2 RSX_RESET
G1 RSX_SPI_CLK RSX SPI Bus
F2 RSX_SPI_DO
F1 RSX_SPI_DI
E2 RSX_SPI_CS