CXD9208GP: Difference between revisions

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Line 27: Line 27:
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23
| data-sort-value="A07" | A7 || {{cellcolors|#8f8}} SIF_RDAC || SIF_RDAC_BC || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A23
|-
|-
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#8f8}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
| data-sort-value="A08" | A8 || data-sort-value="SIF_AD04" {{cellcolors|#afa}} SIF_AD4 || data-sort-value="SIF_BC_AD04" | SIF_BC_AD4 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A19
|-
|-
| data-sort-value="A09" | A9 || data-sort-value="SIF_AD07" {{cellcolors|#8f8}} SIF_AD7 || data-sort-value="SIF_BC_AD07" | SIF_BC_AD7 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C18
| data-sort-value="A09" | A9 || data-sort-value="SIF_AD07" {{cellcolors|#afa}} SIF_AD7 || data-sort-value="SIF_BC_AD07" | SIF_BC_AD7 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C18
|-
|-
| data-sort-value="A10" | A10 || data-sort-value="SIF_AD09" {{cellcolors|#8f8}} SIF_AD9 || data-sort-value="SIF_BC_AD09" | SIF_BC_AD9 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B18
| data-sort-value="A10" | A10 || data-sort-value="SIF_AD09" {{cellcolors|#afa}} SIF_AD9 || data-sort-value="SIF_BC_AD09" | SIF_BC_AD9 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B18
|-
|-
| data-sort-value="A11" | A11 || {{cellcolors|#8f8}} SIF_AD18 || SIF_BC_AD18 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A12
| data-sort-value="A11" | A11 || {{cellcolors|#afa}} SIF_AD18 || SIF_BC_AD18 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A12
|-
|-
| data-sort-value="A12" | A12 || {{cellcolors|#8f8}} SIF_AD21 || SIF_BC_AD21 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C11
| data-sort-value="A12" | A12 || {{cellcolors|#afa}} SIF_AD21 || SIF_BC_AD21 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C11
|-
|-
| data-sort-value="A13" | A13 || {{cellcolors|#8f8}} SIF_AD29 || SIF_BC_AD29 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B9
| data-sort-value="A13" | A13 || {{cellcolors|#afa}} SIF_AD29 || SIF_BC_AD29 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B9
|-
|-
| data-sort-value="A14" | A14 || data-sort-value="SIF_AD06" {{cellcolors|#8f8}} SIF_AD6 || data-sort-value="SIF_BC_AD06" | SIF_BC_AD6 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A18
| data-sort-value="A14" | A14 || data-sort-value="SIF_AD06" {{cellcolors|#afa}} SIF_AD6 || data-sort-value="SIF_BC_AD06" | SIF_BC_AD6 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A18
|-
|-
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="A99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
Line 59: Line 59:
| data-sort-value="B08" | B8 || {{cellcolors|#8f8}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
| data-sort-value="B08" | B8 || {{cellcolors|#8f8}} SIF_BE2 || SIF_BE2_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B21
|-
|-
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#8f8}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
| data-sort-value="B09" | B9 || data-sort-value="SIF_AD01" {{cellcolors|#afa}} SIF_AD1 || data-sort-value="SIF_BC_AD01" | SIF_BC_AD1 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A20
|-
|-
| data-sort-value="B10" | B10 || data-sort-value="SIF_AD03" {{cellcolors|#8f8}} SIF_AD3 || data-sort-value="SIF_BC_AD03" | SIF_BC_AD3 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C19
| data-sort-value="B10" | B10 || data-sort-value="SIF_AD03" {{cellcolors|#afa}} SIF_AD3 || data-sort-value="SIF_BC_AD03" | SIF_BC_AD3 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C19
|-
|-
| data-sort-value="B11" | B11 || {{cellcolors|#8f8}} SIF_AD20 || SIF_BC_AD20 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A11
| data-sort-value="B11" | B11 || {{cellcolors|#afa}} SIF_AD20 || SIF_BC_AD20 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A11
|-
|-
| data-sort-value="B12" | B12 || {{cellcolors|#8f8}} SIF_AD30 || SIF_BC_AD30 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C9
| data-sort-value="B12" | B12 || {{cellcolors|#afa}} SIF_AD30 || SIF_BC_AD30 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C9
|-
|-
| data-sort-value="B13" | B13 || {{cellcolors|#8f8}} SIF_AD26 || SIF_BC_AD26 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A9
| data-sort-value="B13" | B13 || {{cellcolors|#afa}} SIF_AD26 || SIF_BC_AD26 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A9
|-
|-
| data-sort-value="B14" | B14 || {{cellcolors|#8f8}} SIF_AD11 || SIF_BC_AD11 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C15
| data-sort-value="B14" | B14 || {{cellcolors|#afa}} SIF_AD11 || SIF_BC_AD11 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C15
|-
|-
| data-sort-value="B99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="B99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="C01" | C1 || {{cellcolors|#99f}} PCI_AD30 || BC_PCI_AD30 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU31
| data-sort-value="C01" | C1 || {{cellcolors|#bbf}} PCI_AD30 || BC_PCI_AD30 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU31
|-
|-
| data-sort-value="C02" | C2 || {{cellcolors|#99f}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
| data-sort-value="C02" | C2 || {{cellcolors|#bbf}} PCI_AD29 || BC_PCI_AD29 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV31
|-
|-
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C03" | C3 || {{cellcolors|#333|#fff}} TEST_IN_1 || GND || {{pin}} || style="color:#888" | Ground
Line 87: Line 87:
| data-sort-value="C07" | C7 || {{cellcolors|#8f8}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
| data-sort-value="C07" | C7 || {{cellcolors|#8f8}} SIF_BE1 || SIF_BE1_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C22
|-
|-
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#8f8}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
| data-sort-value="C08" | C8 || data-sort-value="SIF_AD02" {{cellcolors|#afa}} SIF_AD2 || data-sort-value="SIF_BC_AD02" | SIF_BC_AD2 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B20
|-
|-
| data-sort-value="C09" | C9 || data-sort-value="SIF_AD00" {{cellcolors|#8f8}} SIF_AD0 || data-sort-value="SIF_BC_AD00" | SIF_BC_AD0 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B19
| data-sort-value="C09" | C9 || data-sort-value="SIF_AD00" {{cellcolors|#afa}} SIF_AD0 || data-sort-value="SIF_BC_AD00" | SIF_BC_AD0 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B19
|-
|-
| data-sort-value="C10" | C10 || {{cellcolors|#8f8}} SIF_AD28 || SIF_BC_AD28 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B12
| data-sort-value="C10" | C10 || {{cellcolors|#afa}} SIF_AD28 || SIF_BC_AD28 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B12
|-
|-
| data-sort-value="C11" | C11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C11" | C11 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 97: Line 97:
| data-sort-value="C12" | C12 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="C12" | C12 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="C13" | C13 || {{cellcolors|#8f8}} SIF_AD31 || SIF_BC_AD31 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A8
| data-sort-value="C13" | C13 || {{cellcolors|#afa}} SIF_AD31 || SIF_BC_AD31 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A8
|-
|-
| data-sort-value="C14" | C14 || {{cellcolors|#8f8}} SIF_AD15 || SIF_BC_AD15 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B15
| data-sort-value="C14" | C14 || {{cellcolors|#afa}} SIF_AD15 || SIF_BC_AD15 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B15
|-
|-
| data-sort-value="C99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="C99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="D01" | D1 || {{cellcolors|#99f}} PCI_AD26 || BC_PCI_AD26 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU30
| data-sort-value="D01" | D1 || {{cellcolors|#bbf}} PCI_AD26 || BC_PCI_AD26 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU30
|-
|-
| data-sort-value="D02" | D2 || {{cellcolors|#99f}} PCI_AD28 || BC_PCI_AD28 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW31
| data-sort-value="D02" | D2 || {{cellcolors|#bbf}} PCI_AD28 || BC_PCI_AD28 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW31
|-
|-
| data-sort-value="D03" | D3 || {{cellcolors|#99f}} PCI_AD31 || BC_PCI_AD31 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT31
| data-sort-value="D03" | D3 || {{cellcolors|#bbf}} PCI_AD31 || BC_PCI_AD31 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT31
|-
|-
| data-sort-value="D04" | D4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="D04" | D4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 125: Line 125:
| data-sort-value="D11" | D11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
| data-sort-value="D11" | D11 || {{cellcolors|#f93|#fff}} VDD || +1.5V_EEGS_VDDO || {{pin}} || Connected to [[Regulators#Mitsumi_MM1561FFBE_.28500_mA_Noise_Reduction_Voltage_Regulator.29 | Mitsumi MM1561FFBE]] (IC6606) pin 1
|-
|-
| data-sort-value="D12" | D12 || {{cellcolors|#8f8}} SIF_AD10 || SIF_BC_AD10 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B16
| data-sort-value="D12" | D12 || {{cellcolors|#afa}} SIF_AD10 || SIF_BC_AD10 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B16
|-
|-
| data-sort-value="D13" | D13 || data-sort-value="SIF_AD05" {{cellcolors|#8f8}} SIF_AD5 || data-sort-value="SIF_BC_AD05" | SIF_BC_AD5 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A17
| data-sort-value="D13" | D13 || data-sort-value="SIF_AD05" {{cellcolors|#afa}} SIF_AD5 || data-sort-value="SIF_BC_AD05" | SIF_BC_AD5 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A17
|-
|-
| data-sort-value="D14" | D14 || {{cellcolors|#8f8}} SIF_AD14 || SIF_BC_AD14 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B14
| data-sort-value="D14" | D14 || {{cellcolors|#afa}} SIF_AD14 || SIF_BC_AD14 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B14
|-
|-
| data-sort-value="D99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="D99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="E01" | E1 || {{cellcolors|#99f}} PCI_AD25 || BC_PCI_AD25 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT29
| data-sort-value="E01" | E1 || {{cellcolors|#bbf}} PCI_AD25 || BC_PCI_AD25 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT29
|-
|-
| data-sort-value="E02" | E2 || {{cellcolors|#99f}} PCI_AD27 || BC_PCI_AD27 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT30
| data-sort-value="E02" | E2 || {{cellcolors|#bbf}} PCI_AD27 || BC_PCI_AD27 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT30
|-
|-
| data-sort-value="E03" | E3 || {{cellcolors|#99f}} PCI_AD24 || BC_PCI_AD24 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU29
| data-sort-value="E03" | E3 || {{cellcolors|#bbf}} PCI_AD24 || BC_PCI_AD24 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU29
|-
|-
| data-sort-value="E04" | E4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E04" | E4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
Line 157: Line 157:
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="E12" | E12 || {{cellcolors|#333|#fff}} TEST_IN_4 || GND || {{pin}} || style="color:#888" | Ground
|-
|-
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#8f8}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
| data-sort-value="E13" | E13 || data-sort-value="SIF_AD08" {{cellcolors|#afa}} SIF_AD8 || data-sort-value="SIF_BC_AD08" | SIF_BC_AD8 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A16
|-
|-
| data-sort-value="E14" | E14 || {{cellcolors|#8f8}} SIF_AD13 || SIF_BC_AD13 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C14
| data-sort-value="E14" | E14 || {{cellcolors|#afa}} SIF_AD13 || SIF_BC_AD13 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C14
|-
|-
| data-sort-value="E99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="E99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="F01" | F1 || {{cellcolors|#99f}} PCI_AD20 || BC_PCI_AD20 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU28
| data-sort-value="F01" | F1 || {{cellcolors|#bbf}} PCI_AD20 || BC_PCI_AD20 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU28
|-
|-
| data-sort-value="F02" | F2 || {{cellcolors|#99f}} PCI_AD22 || BC_PCI_AD22 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW29
| data-sort-value="F02" | F2 || {{cellcolors|#bbf}} PCI_AD22 || BC_PCI_AD22 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW29
|-
|-
| data-sort-value="F03" | F3 || {{cellcolors|#99f}} PCI_AD18 || BC_PCI_AD18 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU27
| data-sort-value="F03" | F3 || {{cellcolors|#bbf}} PCI_AD18 || BC_PCI_AD18 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU27
|-
|-
| data-sort-value="F04" | F4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="F04" | F4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 187: Line 187:
| data-sort-value="F12" | F12 || {{cellcolors|#eee|#888}} GPIO15_0 || CL7306 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="F12" | F12 || {{cellcolors|#eee|#888}} GPIO15_0 || CL7306 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="F13" | F13 || {{cellcolors|#8f8}} SIF_AD12 || SIF_BC_AD12 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A15
| data-sort-value="F13" | F13 || {{cellcolors|#afa}} SIF_AD12 || SIF_BC_AD12 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A15
|-
|-
| data-sort-value="F14" | F14 || {{cellcolors|#8f8}} SIF_AD24 || SIF_BC_AD24 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B11
| data-sort-value="F14" | F14 || {{cellcolors|#afa}} SIF_AD24 || SIF_BC_AD24 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B11
|-
|-
| data-sort-value="F99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="F99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="G01" | G1 || {{cellcolors|#99f}} PCI_AD21 || BC_PCI_AD21 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT28
| data-sort-value="G01" | G1 || {{cellcolors|#bbf}} PCI_AD21 || BC_PCI_AD21 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT28
|-
|-
| data-sort-value="G02" | G2 || {{cellcolors|#99f}} PCI_AD23 || BC_PCI_AD23 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV29
| data-sort-value="G02" | G2 || {{cellcolors|#bbf}} PCI_AD23 || BC_PCI_AD23 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV29
|-
|-
| data-sort-value="G03" | G3 || {{cellcolors|#99f}} PCI_IDSEL || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="G03" | G3 || {{cellcolors|#99f}} PCI_IDSEL || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
Line 217: Line 217:
| data-sort-value="G12" | G12 || {{cellcolors|#eee|#888}} GPIO15_1 || CL7311 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="G12" | G12 || {{cellcolors|#eee|#888}} GPIO15_1 || CL7311 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="G13" | G13 || {{cellcolors|#8f8}} SIF_AD16 || SIF_BC_AD16 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A14
| data-sort-value="G13" | G13 || {{cellcolors|#afa}} SIF_AD16 || SIF_BC_AD16 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A14
|-
|-
| data-sort-value="G14" | G14 || {{cellcolors|#8f8}} SIF_AD23 || SIF_BC_AD23 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A10
| data-sort-value="G14" | G14 || {{cellcolors|#afa}} SIF_AD23 || SIF_BC_AD23 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A10
|-
|-
| data-sort-value="G99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="G99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="H01" | H1 || {{cellcolors|#99f}} PCI_AD15 || BC_PCI_AD15 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT23
| data-sort-value="H01" | H1 || {{cellcolors|#bbf}} PCI_AD15 || BC_PCI_AD15 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT23
|-
|-
| data-sort-value="H02" | H2 || {{cellcolors|#99f}} PCI_AD16 || BC_PCI_AD16 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW27
| data-sort-value="H02" | H2 || {{cellcolors|#bbf}} PCI_AD16 || BC_PCI_AD16 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW27
|-
|-
| data-sort-value="H03" | H3 || {{cellcolors|#99f}} PCI_AD19 || BC_PCI_AD19 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT27
| data-sort-value="H03" | H3 || {{cellcolors|#bbf}} PCI_AD19 || BC_PCI_AD19 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT27
|-
|-
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="H04" | H4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 247: Line 247:
| data-sort-value="H12" | H12 || {{cellcolors|#eee|#888}} GPIO15_2 || CL7305 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="H12" | H12 || {{cellcolors|#eee|#888}} GPIO15_2 || CL7305 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="H13" | H13 || {{cellcolors|#8f8}} SIF_AD22 || SIF_BC_AD22 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C13
| data-sort-value="H13" | H13 || {{cellcolors|#afa}} SIF_AD22 || SIF_BC_AD22 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C13
|-
|-
| data-sort-value="H14" | H14 || {{cellcolors|#8f8}} SIF_AD25 || SIF_BC_AD25 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B10
| data-sort-value="H14" | H14 || {{cellcolors|#afa}} SIF_AD25 || SIF_BC_AD25 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B10
|-
|-
| data-sort-value="H99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="H99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="J01" | J1 || {{cellcolors|#99f}} PCI_AD14 || BC_PCI_AD14 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU23
| data-sort-value="J01" | J1 || {{cellcolors|#bbf}} PCI_AD14 || BC_PCI_AD14 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU23
|-
|-
| data-sort-value="J02" | J2 || {{cellcolors|#99f}} PCI_AD17 || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
| data-sort-value="J02" | J2 || {{cellcolors|#bbf}} PCI_AD17 || BC_PCI_AD17 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV27
|-
|-
| data-sort-value="J03" | J3 || data-sort-value="PCI_AD06" {{cellcolors|#99f}} PCI_AD6 || data-sort-value="BC_PCI_AD06" | BC_PCI_AD6 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW21
| data-sort-value="J03" | J3 || data-sort-value="PCI_AD06" {{cellcolors|#bbf}} PCI_AD6 || data-sort-value="BC_PCI_AD06" | BC_PCI_AD6 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW21
|-
|-
| data-sort-value="J04" | J4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="J04" | J4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 277: Line 277:
| data-sort-value="J12" | J12 || {{cellcolors|#eee|#888}} GPIO33_0 || CL7310 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="J12" | J12 || {{cellcolors|#eee|#888}} GPIO33_0 || CL7310 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="J13" | J13 || {{cellcolors|#8f8}} SIF_AD19 || SIF_BC_AD19 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B13
| data-sort-value="J13" | J13 || {{cellcolors|#afa}} SIF_AD19 || SIF_BC_AD19 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad B13
|-
|-
| data-sort-value="J14" | J14 || {{cellcolors|#8f8}} SIF_AD27 || SIF_BC_AD27 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C10
| data-sort-value="J14" | J14 || {{cellcolors|#afa}} SIF_AD27 || SIF_BC_AD27 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad C10
|-
|-
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="J99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="K01" | K1 || data-sort-value="PCI_AD09" {{cellcolors|#99f}} PCI_AD9 || data-sort-value="BC_PCI_AD09" | BC_PCI_AD9 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT21
| data-sort-value="K01" | K1 || data-sort-value="PCI_AD09" {{cellcolors|#bbf}} PCI_AD9 || data-sort-value="BC_PCI_AD09" | BC_PCI_AD9 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT21
|-
|-
| data-sort-value="K02" | K2 || {{cellcolors|#99f}} PCI_AD11 || BC_PCI_AD11 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT22
| data-sort-value="K02" | K2 || {{cellcolors|#bbf}} PCI_AD11 || BC_PCI_AD11 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT22
|-
|-
| data-sort-value="K03" | K3 || {{cellcolors|#99f}} PCI_AD10 || BC_PCI_AD10 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU22
| data-sort-value="K03" | K3 || {{cellcolors|#bbf}} PCI_AD10 || BC_PCI_AD10 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU22
|-
|-
| data-sort-value="K04" | K4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="K04" | K4 || {{cellcolors|#333|#fff}} VSS || GND || {{pin}} || style="color:#888" | Ground
Line 307: Line 307:
| data-sort-value="K12" | K12 || {{cellcolors|#eee|#888}} GPIO33_1 || CL7304 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
| data-sort-value="K12" | K12 || {{cellcolors|#eee|#888}} GPIO33_1 || CL7304 || {{pinnc}} || data-sort-value="Z" style="color:#888" | Testpad
|-
|-
| data-sort-value="K13" | K13 || {{cellcolors|#8f8}} SIF_AD17 || SIF_BC_AD17 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A13
| data-sort-value="K13" | K13 || {{cellcolors|#afa}} SIF_AD17 || SIF_BC_AD17 || {{pini}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A13
|-
|-
| data-sort-value="K14" | K14 || {{cellcolors|#8f8}} SIF_BREQ || BREQ_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A7
| data-sort-value="K14" | K14 || {{cellcolors|#8f8}} SIF_BREQ || BREQ_BC || {{pino}} || Connected to [[CXD2953AGB | EEGS CXD2953AGB]] pad A7
Line 313: Line 313:
| data-sort-value="K99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="K99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="L01" | L1 || data-sort-value="PCI_AD03" {{cellcolors|#99f}} PCI_AD3 || data-sort-value="BC_PCI_AD03" | BC_PCI_AD3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT19
| data-sort-value="L01" | L1 || data-sort-value="PCI_AD03" {{cellcolors|#bbf}} PCI_AD3 || data-sort-value="BC_PCI_AD03" | BC_PCI_AD3 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT19
|-
|-
| data-sort-value="L02" | L2 || data-sort-value="PCI_AD07" {{cellcolors|#99f}} PCI_AD7 || data-sort-value="BC_PCI_AD07" | BC_PCI_AD7 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV21
| data-sort-value="L02" | L2 || data-sort-value="PCI_AD07" {{cellcolors|#bbf}} PCI_AD7 || data-sort-value="BC_PCI_AD07" | BC_PCI_AD7 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV21
|-
|-
| data-sort-value="L03" | L3 || {{cellcolors|#99f}} PCI_AD13 || BC_PCI_AD13 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV23
| data-sort-value="L03" | L3 || {{cellcolors|#bbf}} PCI_AD13 || BC_PCI_AD13 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV23
|-
|-
| data-sort-value="L04" | L4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="L04" | L4 || {{cellcolors|#e63|#fff}} VDDC || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
Line 343: Line 343:
| data-sort-value="L99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="L99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="M01" | M1 || data-sort-value="PCI_AD04" {{cellcolors|#99f}} PCI_AD4 || data-sort-value="BC_PCI_AD04" | BC_PCI_AD4 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU20
| data-sort-value="M01" | M1 || data-sort-value="PCI_AD04" {{cellcolors|#bbf}} PCI_AD4 || data-sort-value="BC_PCI_AD04" | BC_PCI_AD4 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU20
|-
|-
| data-sort-value="M02" | M2 || data-sort-value="PCI_AD02" {{cellcolors|#99f}} PCI_AD2 || data-sort-value="BC_PCI_AD02" | BC_PCI_AD2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU19
| data-sort-value="M02" | M2 || data-sort-value="PCI_AD02" {{cellcolors|#bbf}} PCI_AD2 || data-sort-value="BC_PCI_AD02" | BC_PCI_AD2 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU19
|-
|-
| data-sort-value="M03" | M3 || data-sort-value="PCI_AD01" {{cellcolors|#99f}} PCI_AD1 || data-sort-value="BC_PCI_AD01" | BC_PCI_AD1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV19
| data-sort-value="M03" | M3 || data-sort-value="PCI_AD01" {{cellcolors|#bbf}} PCI_AD1 || data-sort-value="BC_PCI_AD01" | BC_PCI_AD1 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AV19
|-
|-
| data-sort-value="M04" | M4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="M04" | M4 || {{cellcolors|#333|#fff}} VSS2 || GND || {{pin}} || style="color:#888" | Ground
Line 373: Line 373:
| data-sort-value="M99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="M99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="N01" | N1 || data-sort-value="PCI_AD08" {{cellcolors|#99f}} PCI_AD8 || data-sort-value="BC_PCI_AD08" | BC_PCI_AD8 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU21
| data-sort-value="N01" | N1 || data-sort-value="PCI_AD08" {{cellcolors|#bbf}} PCI_AD8 || data-sort-value="BC_PCI_AD08" | BC_PCI_AD8 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AU21
|-
|-
| data-sort-value="N02" | N2 || data-sort-value="PCI_AD05" {{cellcolors|#99f}} PCI_AD5 || data-sort-value="BC_PCI_AD05" | BC_PCI_AD5 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT20
| data-sort-value="N02" | N2 || data-sort-value="PCI_AD05" {{cellcolors|#bbf}} PCI_AD5 || data-sort-value="BC_PCI_AD05" | BC_PCI_AD5 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT20
|-
|-
| data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
| data-sort-value="N03" | N3 || {{cellcolors|#e63|#fff}} PLLAVD0 || +1.5V_BRIDGE || {{pin}} || Connected to [[Regulators#Mitsumi_MM1591FFBEG_.28Low-Saturation_300mA_Regulators.29 | Mitsumi MM1591FFBEG]] (IC6021) pin 1
|-
|-
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#99f}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
| data-sort-value="N04" | N4 || data-sort-value="PCI_AD00" {{cellcolors|#bbf}} PCI_AD0 || data-sort-value="BC_PCI_AD00" | BC_PCI_AD0 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW19
|-
|-
| data-sort-value="N05" | N5 || {{cellcolors|#99f}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24
| data-sort-value="N05" | N5 || {{cellcolors|#99f}} PCI_SERR || BC_PCI_SERR || {{pino}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AT24
Line 403: Line 403:
| data-sort-value="N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
| data-sort-value="N99" style="padding:0px" | || colspan="4" data-sort-value="ZZZ" style="padding:0px" |  
|-
|-
| data-sort-value="P01" | P1 || {{cellcolors|#99f}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
| data-sort-value="P01" | P1 || {{cellcolors|#bbf}} PCI_AD12 || BC_PCI_AD12 || {{pini}} || Connected to [[South Bridge]] [[CXD2973GB]] pad AW23
|-
|-
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground
| data-sort-value="P02" | P2 || {{cellcolors|#333|#fff}} PLLAVS0 || GND || {{pin}} || style="color:#888" | Ground

Revision as of 10:51, 16 October 2022

Sony CXD9208GP (PS2 bridge chip)

PS2 bridge chip, from EE+GS to South Bridge

6-710-433-01 / IC7301

Used on PS3 FAT CECHAxx/COK-001 and CECHBxx/COK-001
PS2 bridge located in between EE+GS and the South Bridge

Pinout

Pad Name Type Description
Internal External
A1 TEST_IN_0 GND
Others
 Ground
A2 PLLAVS1 GND
Others
 Ground
A3 SIF_MSCLK MSCLK
In
 Connected to EEGS CXD2953AGB pads B8 and A21
A4 SIF_WRAC SIF_WRAC_BC
In
 Connected to EEGS CXD2953AGB pad B23
A5 SIF_DACK SIF_DACK_BC
In
 Connected to EEGS CXD2953AGB pad A25
A6 SIF_DREQ0 SIF_DREQ0_BC
In
 Connected to EEGS CXD2953AGB pad B24
A7 SIF_RDAC SIF_RDAC_BC
In
 Connected to EEGS CXD2953AGB pad A23
A8 SIF_AD4 SIF_BC_AD4
In
 Connected to EEGS CXD2953AGB pad A19
A9 SIF_AD7 SIF_BC_AD7
In
 Connected to EEGS CXD2953AGB pad C18
A10 SIF_AD9 SIF_BC_AD9
In
 Connected to EEGS CXD2953AGB pad B18
A11 SIF_AD18 SIF_BC_AD18
In
 Connected to EEGS CXD2953AGB pad A12
A12 SIF_AD21 SIF_BC_AD21
In
 Connected to EEGS CXD2953AGB pad C11
A13 SIF_AD29 SIF_BC_AD29
In
 Connected to EEGS CXD2953AGB pad B9
A14 SIF_AD6 SIF_BC_AD6
In
 Connected to EEGS CXD2953AGB pad A18
B1 GPIO33_6 CL7307
Not Connected
 Testpad
B2 GPIO33_5 CL7302
Not Connected
 Testpad
B3 PLLAVD1 +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
B4 SIF_SINT SINT_BC
Out
 Connected to EEGS CXD2953AGB pad C21
B5 SIF_BE3 SIF_BE3_BC
Out
 Connected to EEGS CXD2953AGB pad C24
B6 SIF_DREQ1 SIF_DREQ1_BC
In
 Connected to EEGS CXD2953AGB pad A24
B7 SIF_RDY SIF_RDY_BC
In
 Connected to EEGS CXD2953AGB pad A22
B8 SIF_BE2 SIF_BE2_BC
Out
 Connected to EEGS CXD2953AGB pad B21
B9 SIF_AD1 SIF_BC_AD1
In
 Connected to EEGS CXD2953AGB pad A20
B10 SIF_AD3 SIF_BC_AD3
In
 Connected to EEGS CXD2953AGB pad C19
B11 SIF_AD20 SIF_BC_AD20
In
 Connected to EEGS CXD2953AGB pad A11
B12 SIF_AD30 SIF_BC_AD30
In
 Connected to EEGS CXD2953AGB pad C9
B13 SIF_AD26 SIF_BC_AD26
In
 Connected to EEGS CXD2953AGB pad A9
B14 SIF_AD11 SIF_BC_AD11
In
 Connected to EEGS CXD2953AGB pad C15
C1 PCI_AD30 BC_PCI_AD30
In
 Connected to South Bridge CXD2973GB pad AU31
C2 PCI_AD29 BC_PCI_AD29
In
 Connected to South Bridge CXD2973GB pad AV31
C3 TEST_IN_1 GND
Others
 Ground
C4 VSS2 GND
Others
 Ground
C5 VSS2 GND
Others
 Ground
C6 SIF_BE0 SIF_BE0_BC
Out
 Connected to EEGS CXD2953AGB pad B22
C7 SIF_BE1 SIF_BE1_BC
Out
 Connected to EEGS CXD2953AGB pad C22
C8 SIF_AD2 SIF_BC_AD2
In
 Connected to EEGS CXD2953AGB pad B20
C9 SIF_AD0 SIF_BC_AD0
In
 Connected to EEGS CXD2953AGB pad B19
C10 SIF_AD28 SIF_BC_AD28
In
 Connected to EEGS CXD2953AGB pad B12
C11 VSS GND
Others
 Ground
C12 VSS GND
Others
 Ground
C13 SIF_AD31 SIF_BC_AD31
In
 Connected to EEGS CXD2953AGB pad A8
C14 SIF_AD15 SIF_BC_AD15
In
 Connected to EEGS CXD2953AGB pad B15
D1 PCI_AD26 BC_PCI_AD26
In
 Connected to South Bridge CXD2973GB pad AU30
D2 PCI_AD28 BC_PCI_AD28
In
 Connected to South Bridge CXD2973GB pad AW31
D3 PCI_AD31 BC_PCI_AD31
In
 Connected to South Bridge CXD2973GB pad AT31
D4 VSS GND
Others
 Ground
D5 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
D6 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
D7 VSS GND
Others
 Ground
D8 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
D9 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
D10 VSS GND
Others
 Ground
D11 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
D12 SIF_AD10 SIF_BC_AD10
In
 Connected to EEGS CXD2953AGB pad B16
D13 SIF_AD5 SIF_BC_AD5
In
 Connected to EEGS CXD2953AGB pad A17
D14 SIF_AD14 SIF_BC_AD14
In
 Connected to EEGS CXD2953AGB pad B14
E1 PCI_AD25 BC_PCI_AD25
In
 Connected to South Bridge CXD2973GB pad AT29
E2 PCI_AD27 BC_PCI_AD27
In
 Connected to South Bridge CXD2973GB pad AT30
E3 PCI_AD24 BC_PCI_AD24
In
 Connected to South Bridge CXD2973GB pad AU29
E4 VSS2 GND
Others
 Ground
E5 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
E6 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
E7 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
E8 VSS2 GND
Others
 Ground
E9 TEST_IN_3 GND
Others
 Ground
E10 VDD2 +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
E11 VDD2 +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
E12 TEST_IN_4 GND
Others
 Ground
E13 SIF_AD8 SIF_BC_AD8
In
 Connected to EEGS CXD2953AGB pad A16
E14 SIF_AD13 SIF_BC_AD13
In
 Connected to EEGS CXD2953AGB pad C14
F1 PCI_AD20 BC_PCI_AD20
In
 Connected to South Bridge CXD2973GB pad AU28
F2 PCI_AD22 BC_PCI_AD22
In
 Connected to South Bridge CXD2973GB pad AW29
F3 PCI_AD18 BC_PCI_AD18
In
 Connected to South Bridge CXD2973GB pad AU27
F4 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
F5 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
F6 VSS GND
Others
 Ground
F7 VSS GND
Others
 Ground
F8 TEST_IN_2 GND
Others
 Ground
F9 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
F10 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
F11 VSS2 GND
Others
 Ground
F12 GPIO15_0 CL7306
Not Connected
 Testpad
F13 SIF_AD12 SIF_BC_AD12
In
 Connected to EEGS CXD2953AGB pad A15
F14 SIF_AD24 SIF_BC_AD24
In
 Connected to EEGS CXD2953AGB pad B11
G1 PCI_AD21 BC_PCI_AD21
In
 Connected to South Bridge CXD2973GB pad AT28
G2 PCI_AD23 BC_PCI_AD23
In
 Connected to South Bridge CXD2973GB pad AV29
G3 PCI_IDSEL BC_PCI_AD17
In
 Connected to South Bridge CXD2973GB pad AV27
G4 VSS GND
Others
 Ground
G5 VSS2 GND
Others
 Ground
G6 VSS GND
Others
 Ground
G7 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
G8 VDD2 +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
G9 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
G10 VSS2 GND
Others
 Ground
G11 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
G12 GPIO15_1 CL7311
Not Connected
 Testpad
G13 SIF_AD16 SIF_BC_AD16
In
 Connected to EEGS CXD2953AGB pad A14
G14 SIF_AD23 SIF_BC_AD23
In
 Connected to EEGS CXD2953AGB pad A10
H1 PCI_AD15 BC_PCI_AD15
In
 Connected to South Bridge CXD2973GB pad AT23
H2 PCI_AD16 BC_PCI_AD16
In
 Connected to South Bridge CXD2973GB pad AW27
H3 PCI_AD19 BC_PCI_AD19
In
 Connected to South Bridge CXD2973GB pad AT27
H4 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
H5 TEST_PLL_BP_0 GND
Others
 Ground
H6 VSS2 GND
Others
 Ground
H7 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
H8 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
H9 VDD2 +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
H10 VSS GND
Others
 Ground
H11 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
H12 GPIO15_2 CL7305
Not Connected
 Testpad
H13 SIF_AD22 SIF_BC_AD22
In
 Connected to EEGS CXD2953AGB pad C13
H14 SIF_AD25 SIF_BC_AD25
In
 Connected to EEGS CXD2953AGB pad B10
J1 PCI_AD14 BC_PCI_AD14
In
 Connected to South Bridge CXD2973GB pad AU23
J2 PCI_AD17 BC_PCI_AD17
In
 Connected to South Bridge CXD2973GB pad AV27
J3 PCI_AD6 BC_PCI_AD6
In
 Connected to South Bridge CXD2973GB pad AW21
J4 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
J5 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
J6 VSS GND
Others
 Ground
J7 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
J8 VSS GND
Others
 Ground
J9 VSS GND
Others
 Ground
J10 VSS2 GND
Others
 Ground
J11 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
J12 GPIO33_0 CL7310
Not Connected
 Testpad
J13 SIF_AD19 SIF_BC_AD19
In
 Connected to EEGS CXD2953AGB pad B13
J14 SIF_AD27 SIF_BC_AD27
In
 Connected to EEGS CXD2953AGB pad C10
K1 PCI_AD9 BC_PCI_AD9
In
 Connected to South Bridge CXD2973GB pad AT21
K2 PCI_AD11 BC_PCI_AD11
In
 Connected to South Bridge CXD2973GB pad AT22
K3 PCI_AD10 BC_PCI_AD10
In
 Connected to South Bridge CXD2973GB pad AU22
K4 VSS GND
Others
 Ground
K5 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
K6 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
K7 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
K8 TEST_PLL_BP_1 GND
Others
 Ground
K9 VSS GND
Others
 Ground
K10 VDD +1.5V_EEGS_VDDO
Others
 Connected to Mitsumi MM1561FFBE (IC6606) pin 1
K11 VSS GND
Others
 Ground
K12 GPIO33_1 CL7304
Not Connected
 Testpad
K13 SIF_AD17 SIF_BC_AD17
In
 Connected to EEGS CXD2953AGB pad A13
K14 SIF_BREQ BREQ_BC
Out
 Connected to EEGS CXD2953AGB pad A7
L1 PCI_AD3 BC_PCI_AD3
In
 Connected to South Bridge CXD2973GB pad AT19
L2 PCI_AD7 BC_PCI_AD7
In
 Connected to South Bridge CXD2973GB pad AV21
L3 PCI_AD13 BC_PCI_AD13
In
 Connected to South Bridge CXD2973GB pad AV23
L4 VDDC +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
L5 VSS2 GND
Others
 Ground
L6 VSS GND
Others
 Ground
L7 VSS2 GND
Others
 Ground
L8 VSS GND
Others
 Ground
L9 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
L10 VDDS +3.3V_BRIDGE
Others
 Connected to Mitsumi MM1593DFBEG (IC6022) pin 1
L11 VSS GND
Others
 Ground
L12 GPIO33_2 CL7309
Not Connected
 Testpad
L13 SIF_BGNT BGNT_BC
In
 Connected to EEGS CXD2953AGB pad B7
L14 SIF_GINT SGINT_BC
In
 Connected to EEGS CXD2953AGB pad B6
M1 PCI_AD4 BC_PCI_AD4
In
 Connected to South Bridge CXD2973GB pad AU20
M2 PCI_AD2 BC_PCI_AD2
In
 Connected to South Bridge CXD2973GB pad AU19
M3 PCI_AD1 BC_PCI_AD1
In
 Connected to South Bridge CXD2973GB pad AV19
M4 VSS2 GND
Others
 Ground
M5 PCI_STOP BC_PCI_STOP
In
 Connected to South Bridge CXD2973GB pad AV25
M6 PCI_PAR BC_PCI_PAR
In
 Connected to South Bridge CXD2973GB pad AU24
M7 PCI_TRDY BC_PCI_TRDY
In
 Connected to South Bridge CXD2973GB pad AT25
M8 PCI_CBE0 BC_PCI_CBE0
In
 Connected to South Bridge CXD2973GB pad AP19
M9 PCI_FRAME BC_PCI_FRAME
In
 Connected to South Bridge CXD2973GB pad AT26
M10 PCI_RST BC_PCI_RST
In
 Connected to South Bridge CXD2973GB pad AP29 through a 22 ohm resistor
M11 SW1.5 SW1.5
Out
 Connected to Mitsumi MM1561FFBE (IC6606) pin 5 (switches +1.5V_EEGS_VDDO)
M12 GPIO33_3 CL7303
Not Connected
 Testpad
M13 VBLK EEGS_VBLK1
Out
 Connected to EEGS CXD2953AGB pad A4 (Vertical BLanK)
M14 HBLK EEGS_HBLK1
Out
 Connected to EEGS CXD2953AGB pad B5 (Horizontal BLanK)
N1 PCI_AD8 BC_PCI_AD8
In
 Connected to South Bridge CXD2973GB pad AU21
N2 PCI_AD5 BC_PCI_AD5
In
 Connected to South Bridge CXD2973GB pad AT20
N3 PLLAVD0 +1.5V_BRIDGE
Others
 Connected to Mitsumi MM1591FFBEG (IC6021) pin 1
N4 PCI_AD0 BC_PCI_AD0
In
 Connected to South Bridge CXD2973GB pad AW19
N5 PCI_SERR BC_PCI_SERR
Out
 Connected to South Bridge CXD2973GB pad AT24
N6 PCI_DEVSEL BC_PCI_DEVSEL
In
 Connected to South Bridge CXD2973GB pad AU25
N7 PCI_CBE2 BC_PCI_CBE2
In
 Connected to South Bridge CXD2973GB pad AP20
N8 PCI_GNT BC_PCI_GNT1
In
 Connected to South Bridge CXD2973GB pad AN24
N9 SW2.65 SW2.65
Out
 Connected to Mitsumi MM1662YHBE (IC6607) pin 5 (switches +2.5V_RDRAM_VDD)
N10 SW3.3 SW3.3
Out
 Connected to Mitsumi MM1573ENRE (IC6605) pin 3 (switches +3.3V_DRCG_VDD)
N11 SW1.81 SW1.81
Out
 Connected to Mitsumi MM1561JFBE (IC6603) pin 5 (switches +1.8V_EEGS_VDDIO)
N12 GPIO33_4 CL7308
Not Connected
 Testpad
N13 PCLKEN PCLKEN
Out
 Connected to base pin of DTC144EUA-T106 transistor (Q2101) to switch TC7WP3125FK (IC2105) and generate the clock DRCG_GEN18M
DRCG_GEN18M is a input of the Renesas ICS626BGLFT (IC7001) that generates the clocks for the communications in between EEGS and the RDRAM chips (CTMA/CTMNA and CTMB/CTMNB)
N14 EGRST EGRST
Out
 Connected to EEGS CXD2953AGB pad B4 (control line to reset EEGS)
P1 PCI_AD12 BC_PCI_AD12
In
 Connected to South Bridge CXD2973GB pad AW23
P2 PLLAVS0 GND
Others
 Ground
P3 PCI_CLK BC_PCI_CLK
In
 Connected to ICS1493G-18LFT (IC5001) pin 5
Connected to South Bridge CXD2973GB pad AP28 through a 49.9 ohm resistor
P4 PCI_CBE1 BC_PCI_CBE1
In
 Connected to South Bridge CXD2973GB pad AN19
P5 PCI_PERR BC_PCI_PERR
Out
 Connected to South Bridge CXD2973GB pad AW25
P6 PCI_IRDY BC_PCI_IRDY
In
 Connected to South Bridge CXD2973GB pad AU26
P7 PCI_CBE3 BC_PCI_CBE3
In
 Connected to South Bridge CXD2973GB pad AN20
P8 PCI_REQ BC_PCI_REQ1
In
 Connected to South Bridge CXD2973GB pad AN22
P9 SW1.8 SW1.8
Out
 Connected to a missing component (IC6604) pin 3 (switches +1.8V_RDRAM_VCMOS)
P10 SW2.5 SW2.5
Out
 Connected to OnSemi NCP511SN25T1G (IC6601) pin 3 (switches +2.5V_EEGS_PLLVDD1)
P11 SW1.2 SW1.2
Out
 Connected to Rohm BD3504FVM-TR (IC6602) pin 3 (switches +1.2V_EEGS_VDD)
P12 SW3.1 SW3.1
Out
 Connected to Mitsumi MM3143BNRE (IC6600) pin 3 (switches +3.1V_EEGS_AVDA)
P13 GPIO33_7 CL7301
Not Connected
 Testpad
P14 PWRUP_EE PWRUP_EE
Out
 Connected to EEGS CXD2953AGB pad Y1 (control line to power EEGS)
Syscon
CXR713F Series
CELL
90 nm
65 nm
45 nm
RSX
90 nm
65 nm
40 nm
28 nm
CELL RAM
(XDR)
Elpida
Qimonda
Samsung
RSX RAM
(GDDR3 or 5)
Elpida
Infineon & Qimonda
Samsung
Hynix
PS2
Compatibility
EEGS
RDRAM
Bridge
South Bridge
Starship2
Flash
NAND
Samsung
NOR
Macronix
Samsung
Spansion
eMMC
Samsung
Panasonic
BD SATA/PATA
BD Controllers
On BD board
Sony
Renesas SCEI
Integrated
Sony
Renesas SCEI
Others
IDT SCEI
Wireless
Connectors
Other
Diverse Comp.
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