Difference between revisions of "PCIe"

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m (PCIe)
m (PCIe)
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== PCIe ==
 
== PCIe ==
Bus, resembling Conventional PCIe x4 1.0, partly connected to [[South Bridge]], with 200 exposed pads.<br>
+
Bus, resembling [https://en.wikipedia.org/wiki/PCI_Express Conventional PCIe] x4 1.0, partly connected to [[South Bridge]], with 200 exposed pads.<br>
 
Can be activated by setting the [[Repository_Nodes|Repository Node]] ''sys.lv1.iosys.pciex'' to ''1'' (in [[sysctl.txt]]). The PCIe MMIO address space can be extended to 1GB by setting ''sys.lv1.large_pciex'' to ''1''.<br>
 
Can be activated by setting the [[Repository_Nodes|Repository Node]] ''sys.lv1.iosys.pciex'' to ''1'' (in [[sysctl.txt]]). The PCIe MMIO address space can be extended to 1GB by setting ''sys.lv1.large_pciex'' to ''1''.<br>
 
The [[Hypervisor_Reverse_Engineering|Hypervisor]] does not allow all PCIe device to be used with this connector, the check can e.g. be found in ''sub_2355B4'' ([[lv1.self]], [[4.81 DECR]]).
 
The [[Hypervisor_Reverse_Engineering|Hypervisor]] does not allow all PCIe device to be used with this connector, the check can e.g. be found in ''sub_2355B4'' ([[lv1.self]], [[4.81 DECR]]).
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{| class="wikitable sortable"
 
{| class="wikitable sortable"
 
|-
 
|-
! Pin !! Usage !! Standardized Pinout !! Remark
+
! Pin !! Usage !! [https://en.wikipedia.org/wiki/PCI_Express#Pinout Standardized Pinout] !! Remark
 
|-
 
|-
 
| 1  || GND ||  ||
 
| 1  || GND ||  ||

Revision as of 19:27, 21 January 2018

PCIe x4 connector above the Communication Processor (PCI) connector on a TMU-520

PCIe

Bus, resembling Conventional PCIe x4 1.0, partly connected to South Bridge, with 200 exposed pads.
Can be activated by setting the Repository Node sys.lv1.iosys.pciex to 1 (in sysctl.txt). The PCIe MMIO address space can be extended to 1GB by setting sys.lv1.large_pciex to 1.
The Hypervisor does not allow all PCIe device to be used with this connector, the check can e.g. be found in sub_2355B4 (lv1.self, 4.81 DECR).

200-pin layout

CN4351 200P on DECR-1000 TMU-520

Pin Usage Standardized Pinout Remark
1 GND
2 GND
3 ? REFCLK+ ? to clock chip
4 GND
5 ? REFCLK- ? to clock chip
6 GND
7 GND
8 GND
9 GND
10 GND
11 GND
12 GND
13 GND
14 GND
15 PEXPERPA[0] HSIp(0)
16 GND
17 PEXPERNA[0] HSIn(0)
18 GND
19 GND
20 GND
21 GND
22 GND
23 GND
24 GND
25 GND
26 GND
27 PEXPERPA[1] HSIp(1)
28 GND
29 PEXPERNA[1] HSIn(1)
30 GND
31 GND
32 GND
33 GND
34 GND
35 GND
36 GND
37 GND
38 GND
39 PEXPERPA[2] HSIp(2)
40 GND
41 PEXPERNA[2] HSIn(2)
42 GND
43 GND
44 GND
45 GND
46 GND
47 GND
48 GND
49 GND
50 GND
51 PEXPERPA[3] HSIp(3)
52 GND
53 PEXPERNA[3] HSIn(3)
54 GND
55 GND
56 GND
57 GND
58 GND
59 GND
60 GND
61 GND
62 GND
63 PEXPETPA[0] HSOp(0)
64 GND
65 PEXPETNA[0] HSOn(0)
66 GND
67 GND
68 GND
69 GND
70 GND
71 GND
72 GND
73 GND
74 GND
75 PEXPETPA[1] HSOp(1)
76 GND
77 PEXPETNA[1] HSOn(1)
78 GND
79 GND
80 GND
81 GND
82 GND
83 GND
84 GND
85 GND
86 GND
87 PEXPETPA[2] HSOp(2)
88 GND
89 PEXPETNA[2] HSOn(2)
90 GND
91 GND
92 GND
93 GND
94 GND
95 GND
96 GND
97 GND
98 GND
99 PEXPETPA[3] HSOp(3)
100 GND
101 PEXPETPA[3] HSOn(3)
102 GND
103 GND
104 GND
105 GND
106 GND
107 GND
108 GND
109 GND
110 GND
111 GND
112 GND
113 GND
114 GND
115 ? SMDAT ? to smbus chip
116 GND
117 GND
118 GND
119 GND
120 GND
121 GND
122 GND
123 GND
124 GND
125 NC
126 NC
127 +3.3V?
128 +3.3V?
129 NC
130 NC
131 GND
132 GND
133 GND
134 GND
135 GND
136 GND
137 NC
138 NC
139 +3.3V?
140 +3.3V?
141 +3.3V?
142 +3.3V?
143 +3.3V?
144 +3.3V?
145 +3.3V?
146 +3.3V?
147 +3.3V?
148 +3.3V?
149 +3.3V?
150 +3.3V?
151 +3.3V?
152 +3.3V?
153 +3.3V?
154 +3.3V?
155 +3.3V?
156 +3.3V?
157 +3.3V?
158 +3.3V?
159 NC
160 NC
161 +3.3V?
162 +3.3V?
163 +3.3V?
164 +3.3V?
165 +3.3V?
166 +3.3V?
167 NC
168 NC
169 +12V?
170 +12V?
171 +12V?
172 +12V?
173 +12V?
174 +12V?
175 +12V?
176 +12V?
177 +12V?
178 +12V?
179 +12V?
180 +12V?
181 +12V?
182 +12V?
183 +12V?
184 +12V?
185 +12V?
186 +12V?
187 +12V?
188 +12V?
189 +12V?
190 +12V?
191 +12V?
192 +12V?
193 +12V?
194 +12V?
195 NC
196 NC
197 GND
198 GND
199 GND
200 GND